1 /*
2  *
3  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
4  *
5  * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
6  *
7  * See file CREDITS for list of people who contributed to this
8  * project.
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License as
12  * published by the Free Software Foundation; either version 2 of
13  * the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23  * MA 02111-1307 USA
24  */
25 
26 #ifndef __BOARD_MX35_3STACK_H
27 #define __BOARD_MX35_3STACK_H
28 
29 #define AIPS_MPR_CONFIG		0x77777777
30 #define AIPS_OPACR_CONFIG	0x00000000
31 
32 /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
33 #define MAX_MPR_CONFIG		0x00302154
34 /* SGPCR - always park on last master */
35 #define MAX_SGPCR_CONFIG	0x00000010
36 /* MGPCR - restore default values */
37 #define MAX_MGPCR_CONFIG	0x00000000
38 
39 /*
40  * M3IF Control Register (M3IFCTL)
41  * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
42  * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
43  * MRRP[2] = MBX not on priority list (0 << 0)   = 0x00000000
44  * MRRP[3] = MAX1 not on priority list (0 << 0)  = 0x00000000
45  * MRRP[4] = SDMA not on priority list (0 << 0)  = 0x00000000
46  * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
47  * MRRP[6] = IPU1 on priority list (1 << 6)      = 0x00000040
48  * MRRP[7] = IPU2 not on priority list (0 << 0)  = 0x00000000
49  *                                               ------------
50  *                                                 0x00000040
51  */
52 #define M3IF_CONFIG	0x00000040
53 
54 #define DBG_BASE_ADDR		WEIM_CTRL_CS5
55 #define DBG_CSCR_U_CONFIG	0x0000D843
56 #define DBG_CSCR_L_CONFIG	0x22252521
57 #define DBG_CSCR_A_CONFIG	0x22220A00
58 
59 #define CCM_CCMR_CONFIG		0x003F4208
60 #define CCM_PDR0_CONFIG		0x00801000
61 
62 #define PLL_BRM_OFFSET	31
63 #define PLL_PD_OFFSET	26
64 #define PLL_MFD_OFFSET	16
65 #define PLL_MFI_OFFSET	10
66 
67 #define _PLL_BRM(x)	((x) << PLL_BRM_OFFSET)
68 #define _PLL_PD(x)	(((x) - 1) << PLL_PD_OFFSET)
69 #define _PLL_MFD(x)	(((x) - 1) << PLL_MFD_OFFSET)
70 #define _PLL_MFI(x)	((x) << PLL_MFI_OFFSET)
71 #define _PLL_MFN(x)	(x)
72 #define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
73 	(_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
74 	 _PLL_MFN(mfn))
75 
76 #define CCM_MPLL_532_HZ	_PLL_SETTING(1, 1, 12, 11, 1)
77 #define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
78 #define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
79 
80 /* MEMORY SETTING */
81 #define ESDCTL_0x92220000	0x92220000
82 #define ESDCTL_0xA2220000	0xA2220000
83 #define ESDCTL_0xB2220000	0xB2220000
84 #define ESDCTL_0x82228080	0x82228080
85 
86 #define ESDCTL_PRECHARGE	0x00000400
87 
88 #define ESDCTL_MDDR_CONFIG	0x007FFC3F
89 #define ESDCTL_MDDR_MR		0x00000033
90 #define ESDCTL_MDDR_EMR		0x02000000
91 
92 #define ESDCTL_DDR2_CONFIG	0x007FFC3F
93 #define ESDCTL_DDR2_EMR2	0x04000000
94 #define ESDCTL_DDR2_EMR3	0x06000000
95 #define ESDCTL_DDR2_EN_DLL	0x02000400
96 #define ESDCTL_DDR2_RESET_DLL	0x00000333
97 #define ESDCTL_DDR2_MR		0x00000233
98 #define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
99 
100 #define ESDCTL_DELAY_LINE5	0x00F49F00
101 #endif				/* __BOARD_MX35_3STACK_H */
102