1 /*
2  * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
3  *
4  * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24 
25 #include <common.h>
26 #include <asm/io.h>
27 #include <asm/errno.h>
28 #include <asm/arch/imx-regs.h>
29 #include <asm/arch/crm_regs.h>
30 #include <asm/arch/mx35_pins.h>
31 #include <asm/arch/iomux.h>
32 #include <i2c.h>
33 #include <fsl_pmic.h>
34 #include <mc9sdz60.h>
35 #include <mc13892.h>
36 #include <linux/types.h>
37 #include <asm/gpio.h>
38 #include <asm/arch/sys_proto.h>
39 #include <netdev.h>
40 
41 #ifndef BOARD_LATE_INIT
42 #error "BOARD_LATE_INIT must be set for this board"
43 #endif
44 
45 #ifndef CONFIG_BOARD_EARLY_INIT_F
46 #error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
47 #endif
48 
49 #define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); })
50 
51 DECLARE_GLOBAL_DATA_PTR;
52 
53 int dram_init(void)
54 {
55 	u32 size1, size2;
56 
57 	size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
58 	size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
59 
60 	gd->ram_size = size1 + size2;
61 
62 	return 0;
63 }
64 
65 void dram_init_banksize(void)
66 {
67 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
68 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
69 
70 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
71 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
72 }
73 
74 static void setup_iomux_i2c(void)
75 {
76 	int pad;
77 
78 	/* setup pins for I2C1 */
79 	mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
80 	mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
81 
82 	pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
83 			| PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
84 
85 	mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
86 	mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
87 }
88 
89 
90 static void setup_iomux_spi(void)
91 {
92 	mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
93 	mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
94 	mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
95 	mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
96 	mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
97 }
98 
99 static void setup_iomux_fec(void)
100 {
101 	int pad;
102 
103 	/* setup pins for FEC */
104 	mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
105 	mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
106 	mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
107 	mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
108 	mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
109 	mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
110 	mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
111 	mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
112 	mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
113 	mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
114 	mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
115 	mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
116 	mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
117 	mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
118 	mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
119 	mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
120 	mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
121 	mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
122 
123 	pad = (PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | \
124 			PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW);
125 
126 	mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
127 			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
128 	mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
129 			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
130 	mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, pad | PAD_CTL_HYS_SCHMITZ | \
131 			 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
132 	mxc_iomux_set_pad(MX35_PIN_FEC_COL, pad | PAD_CTL_HYS_SCHMITZ | \
133 			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
134 	mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, pad | PAD_CTL_HYS_SCHMITZ | \
135 			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
136 	mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, pad | PAD_CTL_HYS_CMOS | \
137 			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
138 	mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, pad | PAD_CTL_HYS_CMOS | \
139 			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
140 	mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad | PAD_CTL_HYS_CMOS | \
141 			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
142 	mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad | PAD_CTL_HYS_SCHMITZ | \
143 			  PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU);
144 	mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, pad | PAD_CTL_HYS_CMOS | \
145 			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
146 	mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, pad | PAD_CTL_HYS_SCHMITZ | \
147 			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
148 	mxc_iomux_set_pad(MX35_PIN_FEC_CRS, pad | PAD_CTL_HYS_SCHMITZ | \
149 			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
150 	mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, pad | PAD_CTL_HYS_SCHMITZ | \
151 			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
152 	mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, pad | PAD_CTL_HYS_CMOS | \
153 			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
154 	mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, pad | PAD_CTL_HYS_SCHMITZ | \
155 			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
156 	mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, pad | PAD_CTL_HYS_CMOS | \
157 			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
158 	mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, pad | PAD_CTL_HYS_SCHMITZ | \
159 			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
160 	mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, pad | PAD_CTL_HYS_CMOS | \
161 			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
162 }
163 
164 int board_early_init_f(void)
165 {
166 	struct ccm_regs *ccm =
167 		(struct ccm_regs *)IMX_CCM_BASE;
168 
169 	/* enable clocks */
170 	writel(readl(&ccm->cgr0) |
171 		MXC_CCM_CGR0_EMI_MASK |
172 		MXC_CCM_CGR0_EDI0_MASK |
173 		MXC_CCM_CGR0_EPIT1_MASK,
174 		&ccm->cgr0);
175 
176 	writel(readl(&ccm->cgr1) |
177 		MXC_CCM_CGR1_FEC_MASK |
178 		MXC_CCM_CGR1_GPIO1_MASK |
179 		MXC_CCM_CGR1_GPIO2_MASK |
180 		MXC_CCM_CGR1_GPIO3_MASK |
181 		MXC_CCM_CGR1_I2C1_MASK |
182 		MXC_CCM_CGR1_I2C2_MASK |
183 		MXC_CCM_CGR1_IPU_MASK,
184 		&ccm->cgr1);
185 
186 	/* Setup NAND */
187 	__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
188 
189 	setup_iomux_i2c();
190 	setup_iomux_fec();
191 	setup_iomux_spi();
192 
193 	return 0;
194 }
195 
196 int board_init(void)
197 {
198 	gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS;	/* board id for linux */
199 	/* address of boot parameters */
200 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
201 
202 	return 0;
203 }
204 
205 static inline int pmic_detect(void)
206 {
207 	int id;
208 
209 	id = pmic_reg_read(REG_IDENTIFICATION);
210 
211 	id = (id >> 6) & 0x7;
212 	if (id == 0x7)
213 		return 1;
214 	return 0;
215 }
216 
217 u32 get_board_rev(void)
218 {
219 	int rev;
220 
221 	rev = pmic_detect();
222 
223 	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
224 }
225 
226 int board_late_init(void)
227 {
228 	u8 val;
229 	u32 pmic_val;
230 
231 	if (pmic_detect()) {
232 		mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION |
233 					MUX_CONFIG_ALT1);
234 
235 		pmic_val = pmic_reg_read(REG_SETTING_0);
236 		pmic_reg_write(REG_SETTING_0, pmic_val | VO_1_30V | VO_1_50V);
237 		pmic_val = pmic_reg_read(REG_MODE_0);
238 		pmic_reg_write(REG_MODE_0, pmic_val | VGEN3EN);
239 
240 		mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO);
241 		mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0);
242 
243 		gpio_direction_output(37, 1);
244 	}
245 
246 	val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
247 	mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val);
248 	mdelay(200);
249 
250 	val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F;
251 	mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
252 	mdelay(200);
253 
254 	val |= 0x80;
255 	mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
256 
257 	return 0;
258 }
259 
260 int checkboard(void)
261 {
262 	struct ccm_regs *ccm =
263 		(struct ccm_regs *)IMX_CCM_BASE;
264 	u32 cpu_rev = get_cpu_rev();
265 
266 	/*
267 	 * Be sure that I2C is initialized to check
268 	 * the board revision
269 	 */
270 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
271 
272 	/* Print board revision */
273 	printf("Board: MX35 PDK %d.0 ", ((get_board_rev() >> 8) + 1) & 0x0F);
274 
275 	/* Print CPU revision */
276 	printf("i.MX35 %d.%d [", (cpu_rev & 0xF0) >> 4, cpu_rev & 0x0F);
277 
278 	switch (readl(&ccm->rcsr) & 0x0F) {
279 	case 0x0000:
280 		puts("POR");
281 		break;
282 	case 0x0002:
283 		puts("JTAG");
284 		break;
285 	case 0x0004:
286 		puts("RST");
287 		break;
288 	case 0x0008:
289 		puts("WDT");
290 		break;
291 	default:
292 		puts("unknown");
293 	}
294 	puts("]\n");
295 
296 	return 0;
297 }
298 
299 int board_eth_init(bd_t *bis)
300 {
301 	int rc = -ENODEV;
302 #if defined(CONFIG_SMC911X)
303 	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
304 #endif
305 
306 	cpu_eth_init(bis);
307 
308 	return rc;
309 }
310