1 /* 2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> 3 * 4 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <asm/io.h> 27 #include <asm/errno.h> 28 #include <asm/arch/imx-regs.h> 29 #include <asm/arch/crm_regs.h> 30 #include <asm/arch/clock.h> 31 #include <asm/arch/mx35_pins.h> 32 #include <asm/arch/iomux.h> 33 #include <i2c.h> 34 #include <power/pmic.h> 35 #include <fsl_pmic.h> 36 #include <mmc.h> 37 #include <fsl_esdhc.h> 38 #include <mc9sdz60.h> 39 #include <mc13892.h> 40 #include <linux/types.h> 41 #include <asm/gpio.h> 42 #include <asm/arch/sys_proto.h> 43 #include <netdev.h> 44 45 #ifndef CONFIG_BOARD_LATE_INIT 46 #error "CONFIG_BOARD_LATE_INIT must be set for this board" 47 #endif 48 49 #ifndef CONFIG_BOARD_EARLY_INIT_F 50 #error "CONFIG_BOARD_EARLY_INIT_F must be set for this board" 51 #endif 52 53 DECLARE_GLOBAL_DATA_PTR; 54 55 int dram_init(void) 56 { 57 u32 size1, size2; 58 59 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 60 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); 61 62 gd->ram_size = size1 + size2; 63 64 return 0; 65 } 66 67 void dram_init_banksize(void) 68 { 69 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 70 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 71 72 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 73 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 74 } 75 76 static void setup_iomux_i2c(void) 77 { 78 int pad; 79 80 /* setup pins for I2C1 */ 81 mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION); 82 mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION); 83 84 pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \ 85 | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain); 86 87 mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad); 88 mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad); 89 } 90 91 92 static void setup_iomux_spi(void) 93 { 94 mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION); 95 mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION); 96 mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION); 97 mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION); 98 mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION); 99 } 100 101 static void setup_iomux_fec(void) 102 { 103 int pad; 104 105 /* setup pins for FEC */ 106 mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC); 107 mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC); 108 mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC); 109 mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC); 110 mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC); 111 mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC); 112 mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC); 113 mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC); 114 mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC); 115 mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC); 116 mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC); 117 mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC); 118 mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC); 119 mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC); 120 mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC); 121 mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC); 122 mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC); 123 mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC); 124 125 pad = (PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | \ 126 PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW); 127 128 mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \ 129 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 130 mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \ 131 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 132 mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, pad | PAD_CTL_HYS_SCHMITZ | \ 133 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 134 mxc_iomux_set_pad(MX35_PIN_FEC_COL, pad | PAD_CTL_HYS_SCHMITZ | \ 135 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 136 mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, pad | PAD_CTL_HYS_SCHMITZ | \ 137 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 138 mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, pad | PAD_CTL_HYS_CMOS | \ 139 PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); 140 mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, pad | PAD_CTL_HYS_CMOS | \ 141 PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); 142 mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad | PAD_CTL_HYS_CMOS | \ 143 PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); 144 mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad | PAD_CTL_HYS_SCHMITZ | \ 145 PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU); 146 mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, pad | PAD_CTL_HYS_CMOS | \ 147 PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); 148 mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, pad | PAD_CTL_HYS_SCHMITZ | \ 149 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 150 mxc_iomux_set_pad(MX35_PIN_FEC_CRS, pad | PAD_CTL_HYS_SCHMITZ | \ 151 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 152 mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, pad | PAD_CTL_HYS_SCHMITZ | \ 153 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 154 mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, pad | PAD_CTL_HYS_CMOS | \ 155 PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); 156 mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, pad | PAD_CTL_HYS_SCHMITZ | \ 157 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 158 mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, pad | PAD_CTL_HYS_CMOS | \ 159 PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); 160 mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, pad | PAD_CTL_HYS_SCHMITZ | \ 161 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 162 mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, pad | PAD_CTL_HYS_CMOS | \ 163 PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); 164 } 165 166 int board_early_init_f(void) 167 { 168 struct ccm_regs *ccm = 169 (struct ccm_regs *)IMX_CCM_BASE; 170 171 /* enable clocks */ 172 writel(readl(&ccm->cgr0) | 173 MXC_CCM_CGR0_EMI_MASK | 174 MXC_CCM_CGR0_EDIO_MASK | 175 MXC_CCM_CGR0_EPIT1_MASK, 176 &ccm->cgr0); 177 178 writel(readl(&ccm->cgr1) | 179 MXC_CCM_CGR1_FEC_MASK | 180 MXC_CCM_CGR1_GPIO1_MASK | 181 MXC_CCM_CGR1_GPIO2_MASK | 182 MXC_CCM_CGR1_GPIO3_MASK | 183 MXC_CCM_CGR1_I2C1_MASK | 184 MXC_CCM_CGR1_I2C2_MASK | 185 MXC_CCM_CGR1_IPU_MASK, 186 &ccm->cgr1); 187 188 /* Setup NAND */ 189 __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); 190 191 setup_iomux_i2c(); 192 setup_iomux_fec(); 193 setup_iomux_spi(); 194 195 return 0; 196 } 197 198 int board_init(void) 199 { 200 gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */ 201 /* address of boot parameters */ 202 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 203 204 return 0; 205 } 206 207 static inline int pmic_detect(void) 208 { 209 unsigned int id; 210 struct pmic *p = pmic_get("FSL_PMIC"); 211 if (!p) 212 return -ENODEV; 213 214 pmic_reg_read(p, REG_IDENTIFICATION, &id); 215 216 id = (id >> 6) & 0x7; 217 if (id == 0x7) 218 return 1; 219 return 0; 220 } 221 222 u32 get_board_rev(void) 223 { 224 int rev; 225 226 rev = pmic_detect(); 227 228 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; 229 } 230 231 int board_late_init(void) 232 { 233 u8 val; 234 u32 pmic_val; 235 struct pmic *p; 236 int ret; 237 238 ret = pmic_init(I2C_PMIC); 239 if (ret) 240 return ret; 241 242 if (pmic_detect()) { 243 p = pmic_get("FSL_PMIC"); 244 mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION | 245 MUX_CONFIG_ALT1); 246 247 pmic_reg_read(p, REG_SETTING_0, &pmic_val); 248 pmic_reg_write(p, REG_SETTING_0, 249 pmic_val | VO_1_30V | VO_1_50V); 250 pmic_reg_read(p, REG_MODE_0, &pmic_val); 251 pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN); 252 253 mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO); 254 mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0); 255 256 gpio_direction_output(37, 1); 257 } 258 259 val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04; 260 mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val); 261 mdelay(200); 262 263 val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F; 264 mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val); 265 mdelay(200); 266 267 val |= 0x80; 268 mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val); 269 270 /* Print board revision */ 271 printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F); 272 273 return 0; 274 } 275 276 int board_eth_init(bd_t *bis) 277 { 278 int rc = -ENODEV; 279 #if defined(CONFIG_SMC911X) 280 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 281 #endif 282 283 cpu_eth_init(bis); 284 285 return rc; 286 } 287 288 #if defined(CONFIG_FSL_ESDHC) 289 290 struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR}; 291 292 int board_mmc_init(bd_t *bis) 293 { 294 /* configure pins for SDHC1 only */ 295 mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC); 296 mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC); 297 mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC); 298 mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC); 299 mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC); 300 mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC); 301 302 esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); 303 return fsl_esdhc_initialize(bis, &esdhc_cfg); 304 } 305 306 int board_mmc_getcd(struct mmc *mmc) 307 { 308 return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4); 309 } 310 #endif 311