1 /* 2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> 3 * 4 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <asm/io.h> 27 #include <asm/errno.h> 28 #include <asm/arch/imx-regs.h> 29 #include <asm/arch/crm_regs.h> 30 #include <asm/arch/mx35_pins.h> 31 #include <asm/arch/iomux.h> 32 #include <i2c.h> 33 #include <fsl_pmic.h> 34 #include <mc9sdz60.h> 35 #include <mc13892.h> 36 #include <linux/types.h> 37 #include <mxc_gpio.h> 38 #include <asm/arch/sys_proto.h> 39 #include <netdev.h> 40 41 #ifndef BOARD_LATE_INIT 42 #error "BOARD_LATE_INIT must be set for this board" 43 #endif 44 45 #ifndef CONFIG_BOARD_EARLY_INIT_F 46 #error "CONFIG_BOARD_EARLY_INIT_F must be set for this board" 47 #endif 48 49 #define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); }) 50 51 DECLARE_GLOBAL_DATA_PTR; 52 53 int dram_init(void) 54 { 55 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, 56 PHYS_SDRAM_1_SIZE); 57 58 return 0; 59 } 60 61 static void setup_iomux_i2c(void) 62 { 63 int pad; 64 65 /* setup pins for I2C1 */ 66 mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION); 67 mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION); 68 69 pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \ 70 | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain); 71 72 mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad); 73 mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad); 74 } 75 76 77 static void setup_iomux_spi(void) 78 { 79 mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION); 80 mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION); 81 mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION); 82 mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION); 83 mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION); 84 } 85 86 static void setup_iomux_fec(void) 87 { 88 int pad; 89 90 /* setup pins for FEC */ 91 mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC); 92 mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC); 93 mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC); 94 mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC); 95 mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC); 96 mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC); 97 mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC); 98 mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC); 99 mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC); 100 mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC); 101 mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC); 102 mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC); 103 mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC); 104 mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC); 105 mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC); 106 mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC); 107 mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC); 108 mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC); 109 110 pad = (PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | \ 111 PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW); 112 113 mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \ 114 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 115 mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \ 116 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 117 mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, pad | PAD_CTL_HYS_SCHMITZ | \ 118 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 119 mxc_iomux_set_pad(MX35_PIN_FEC_COL, pad | PAD_CTL_HYS_SCHMITZ | \ 120 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 121 mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, pad | PAD_CTL_HYS_SCHMITZ | \ 122 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 123 mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, pad | PAD_CTL_HYS_CMOS | \ 124 PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); 125 mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, pad | PAD_CTL_HYS_CMOS | \ 126 PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); 127 mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad | PAD_CTL_HYS_CMOS | \ 128 PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); 129 mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad | PAD_CTL_HYS_SCHMITZ | \ 130 PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU); 131 mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, pad | PAD_CTL_HYS_CMOS | \ 132 PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); 133 mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, pad | PAD_CTL_HYS_SCHMITZ | \ 134 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 135 mxc_iomux_set_pad(MX35_PIN_FEC_CRS, pad | PAD_CTL_HYS_SCHMITZ | \ 136 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 137 mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, pad | PAD_CTL_HYS_SCHMITZ | \ 138 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 139 mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, pad | PAD_CTL_HYS_CMOS | \ 140 PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); 141 mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, pad | PAD_CTL_HYS_SCHMITZ | \ 142 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 143 mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, pad | PAD_CTL_HYS_CMOS | \ 144 PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); 145 mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, pad | PAD_CTL_HYS_SCHMITZ | \ 146 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 147 mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, pad | PAD_CTL_HYS_CMOS | \ 148 PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); 149 } 150 151 int board_early_init_f(void) 152 { 153 struct ccm_regs *ccm = 154 (struct ccm_regs *)IMX_CCM_BASE; 155 156 /* enable clocks */ 157 writel(readl(&ccm->cgr0) | 158 MXC_CCM_CGR0_EMI_MASK | 159 MXC_CCM_CGR0_EDI0_MASK | 160 MXC_CCM_CGR0_EPIT1_MASK, 161 &ccm->cgr0); 162 163 writel(readl(&ccm->cgr1) | 164 MXC_CCM_CGR1_FEC_MASK | 165 MXC_CCM_CGR1_GPIO1_MASK | 166 MXC_CCM_CGR1_GPIO2_MASK | 167 MXC_CCM_CGR1_GPIO3_MASK | 168 MXC_CCM_CGR1_I2C1_MASK | 169 MXC_CCM_CGR1_I2C2_MASK | 170 MXC_CCM_CGR1_IPU_MASK, 171 &ccm->cgr1); 172 173 /* Setup NAND */ 174 __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); 175 176 setup_iomux_i2c(); 177 setup_iomux_fec(); 178 setup_iomux_spi(); 179 180 return 0; 181 } 182 183 int board_init(void) 184 { 185 gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */ 186 /* address of boot parameters */ 187 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 188 189 return 0; 190 } 191 192 static inline int pmic_detect(void) 193 { 194 int id; 195 196 id = pmic_reg_read(REG_IDENTIFICATION); 197 198 id = (id >> 6) & 0x7; 199 if (id == 0x7) 200 return 1; 201 return 0; 202 } 203 204 u32 get_board_rev(void) 205 { 206 int rev; 207 208 rev = pmic_detect(); 209 210 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; 211 } 212 213 int board_late_init(void) 214 { 215 u8 val; 216 u32 pmic_val; 217 218 if (pmic_detect()) { 219 mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION | 220 MUX_CONFIG_ALT1); 221 222 pmic_val = pmic_reg_read(REG_SETTING_0); 223 pmic_reg_write(REG_SETTING_0, pmic_val | VO_1_30V | VO_1_50V); 224 pmic_val = pmic_reg_read(REG_MODE_0); 225 pmic_reg_write(REG_MODE_0, pmic_val | VGEN3EN); 226 227 mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO); 228 mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0); 229 230 mxc_gpio_direction(37, MXC_GPIO_DIRECTION_OUT); 231 mxc_gpio_set(37, 1); 232 } 233 234 val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04; 235 mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val); 236 mdelay(200); 237 238 val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F; 239 mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val); 240 mdelay(200); 241 242 val |= 0x80; 243 mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val); 244 245 return 0; 246 } 247 248 int checkboard(void) 249 { 250 struct ccm_regs *ccm = 251 (struct ccm_regs *)IMX_CCM_BASE; 252 u32 cpu_rev = get_cpu_rev(); 253 254 /* 255 * Be sure that I2C is initialized to check 256 * the board revision 257 */ 258 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 259 260 /* Print board revision */ 261 printf("Board: MX35 PDK %d.0 ", ((get_board_rev() >> 8) + 1) & 0x0F); 262 263 /* Print CPU revision */ 264 printf("i.MX35 %d.%d [", (cpu_rev & 0xF0) >> 4, cpu_rev & 0x0F); 265 266 switch (readl(&ccm->rcsr) & 0x0F) { 267 case 0x0000: 268 puts("POR"); 269 break; 270 case 0x0002: 271 puts("JTAG"); 272 break; 273 case 0x0004: 274 puts("RST"); 275 break; 276 case 0x0008: 277 puts("WDT"); 278 break; 279 default: 280 puts("unknown"); 281 } 282 puts("]\n"); 283 284 return 0; 285 } 286 287 int board_eth_init(bd_t *bis) 288 { 289 int rc = -ENODEV; 290 #if defined(CONFIG_SMC911X) 291 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 292 #endif 293 294 cpu_eth_init(bis); 295 296 return rc; 297 } 298