1 /*
2  * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
3  *
4  * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24 
25 #include <common.h>
26 #include <asm/io.h>
27 #include <asm/errno.h>
28 #include <asm/arch/imx-regs.h>
29 #include <asm/arch/crm_regs.h>
30 #include <asm/arch/mx35_pins.h>
31 #include <asm/arch/iomux.h>
32 #include <i2c.h>
33 #include <pmic.h>
34 #include <fsl_pmic.h>
35 #include <mc9sdz60.h>
36 #include <mc13892.h>
37 #include <linux/types.h>
38 #include <asm/gpio.h>
39 #include <asm/arch/sys_proto.h>
40 #include <netdev.h>
41 
42 #ifndef BOARD_LATE_INIT
43 #error "BOARD_LATE_INIT must be set for this board"
44 #endif
45 
46 #ifndef CONFIG_BOARD_EARLY_INIT_F
47 #error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
48 #endif
49 
50 DECLARE_GLOBAL_DATA_PTR;
51 
52 int dram_init(void)
53 {
54 	u32 size1, size2;
55 
56 	size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
57 	size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
58 
59 	gd->ram_size = size1 + size2;
60 
61 	return 0;
62 }
63 
64 void dram_init_banksize(void)
65 {
66 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
67 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
68 
69 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
70 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
71 }
72 
73 static void setup_iomux_i2c(void)
74 {
75 	int pad;
76 
77 	/* setup pins for I2C1 */
78 	mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
79 	mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
80 
81 	pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
82 			| PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
83 
84 	mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
85 	mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
86 }
87 
88 
89 static void setup_iomux_spi(void)
90 {
91 	mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
92 	mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
93 	mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
94 	mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
95 	mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
96 }
97 
98 static void setup_iomux_fec(void)
99 {
100 	int pad;
101 
102 	/* setup pins for FEC */
103 	mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
104 	mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
105 	mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
106 	mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
107 	mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
108 	mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
109 	mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
110 	mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
111 	mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
112 	mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
113 	mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
114 	mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
115 	mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
116 	mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
117 	mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
118 	mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
119 	mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
120 	mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
121 
122 	pad = (PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | \
123 			PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW);
124 
125 	mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
126 			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
127 	mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
128 			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
129 	mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, pad | PAD_CTL_HYS_SCHMITZ | \
130 			 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
131 	mxc_iomux_set_pad(MX35_PIN_FEC_COL, pad | PAD_CTL_HYS_SCHMITZ | \
132 			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
133 	mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, pad | PAD_CTL_HYS_SCHMITZ | \
134 			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
135 	mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, pad | PAD_CTL_HYS_CMOS | \
136 			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
137 	mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, pad | PAD_CTL_HYS_CMOS | \
138 			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
139 	mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad | PAD_CTL_HYS_CMOS | \
140 			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
141 	mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad | PAD_CTL_HYS_SCHMITZ | \
142 			  PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU);
143 	mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, pad | PAD_CTL_HYS_CMOS | \
144 			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
145 	mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, pad | PAD_CTL_HYS_SCHMITZ | \
146 			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
147 	mxc_iomux_set_pad(MX35_PIN_FEC_CRS, pad | PAD_CTL_HYS_SCHMITZ | \
148 			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
149 	mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, pad | PAD_CTL_HYS_SCHMITZ | \
150 			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
151 	mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, pad | PAD_CTL_HYS_CMOS | \
152 			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
153 	mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, pad | PAD_CTL_HYS_SCHMITZ | \
154 			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
155 	mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, pad | PAD_CTL_HYS_CMOS | \
156 			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
157 	mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, pad | PAD_CTL_HYS_SCHMITZ | \
158 			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
159 	mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, pad | PAD_CTL_HYS_CMOS | \
160 			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
161 }
162 
163 int board_early_init_f(void)
164 {
165 	struct ccm_regs *ccm =
166 		(struct ccm_regs *)IMX_CCM_BASE;
167 
168 	/* enable clocks */
169 	writel(readl(&ccm->cgr0) |
170 		MXC_CCM_CGR0_EMI_MASK |
171 		MXC_CCM_CGR0_EDI0_MASK |
172 		MXC_CCM_CGR0_EPIT1_MASK,
173 		&ccm->cgr0);
174 
175 	writel(readl(&ccm->cgr1) |
176 		MXC_CCM_CGR1_FEC_MASK |
177 		MXC_CCM_CGR1_GPIO1_MASK |
178 		MXC_CCM_CGR1_GPIO2_MASK |
179 		MXC_CCM_CGR1_GPIO3_MASK |
180 		MXC_CCM_CGR1_I2C1_MASK |
181 		MXC_CCM_CGR1_I2C2_MASK |
182 		MXC_CCM_CGR1_IPU_MASK,
183 		&ccm->cgr1);
184 
185 	/* Setup NAND */
186 	__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
187 
188 	setup_iomux_i2c();
189 	setup_iomux_fec();
190 	setup_iomux_spi();
191 
192 	return 0;
193 }
194 
195 int board_init(void)
196 {
197 	gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS;	/* board id for linux */
198 	/* address of boot parameters */
199 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
200 
201 	return 0;
202 }
203 
204 static inline int pmic_detect(void)
205 {
206 	unsigned int id;
207 	struct pmic *p = get_pmic();
208 
209 	pmic_reg_read(p, REG_IDENTIFICATION, &id);
210 
211 	id = (id >> 6) & 0x7;
212 	if (id == 0x7)
213 		return 1;
214 	return 0;
215 }
216 
217 u32 get_board_rev(void)
218 {
219 	int rev;
220 
221 	rev = pmic_detect();
222 
223 	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
224 }
225 
226 int board_late_init(void)
227 {
228 	u8 val;
229 	u32 pmic_val;
230 	struct pmic *p;
231 
232 	pmic_init();
233 	if (pmic_detect()) {
234 		p = get_pmic();
235 		mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION |
236 					MUX_CONFIG_ALT1);
237 
238 		pmic_reg_read(p, REG_SETTING_0, &pmic_val);
239 		pmic_reg_write(p, REG_SETTING_0,
240 			pmic_val | VO_1_30V | VO_1_50V);
241 		pmic_reg_read(p, REG_MODE_0, &pmic_val);
242 		pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN);
243 
244 		mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO);
245 		mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0);
246 
247 		gpio_direction_output(37, 1);
248 	}
249 
250 	val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
251 	mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val);
252 	mdelay(200);
253 
254 	val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F;
255 	mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
256 	mdelay(200);
257 
258 	val |= 0x80;
259 	mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
260 
261 	return 0;
262 }
263 
264 int checkboard(void)
265 {
266 	struct ccm_regs *ccm =
267 		(struct ccm_regs *)IMX_CCM_BASE;
268 	u32 cpu_rev = get_cpu_rev();
269 
270 	/*
271 	 * Be sure that I2C is initialized to check
272 	 * the board revision
273 	 */
274 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
275 
276 	/* Print board revision */
277 	printf("Board: MX35 PDK %d.0 ", ((get_board_rev() >> 8) + 1) & 0x0F);
278 
279 	/* Print CPU revision */
280 	printf("i.MX35 %d.%d [", (cpu_rev & 0xF0) >> 4, cpu_rev & 0x0F);
281 
282 	switch (readl(&ccm->rcsr) & 0x0F) {
283 	case 0x0000:
284 		puts("POR");
285 		break;
286 	case 0x0002:
287 		puts("JTAG");
288 		break;
289 	case 0x0004:
290 		puts("RST");
291 		break;
292 	case 0x0008:
293 		puts("WDT");
294 		break;
295 	default:
296 		puts("unknown");
297 	}
298 	puts("]\n");
299 
300 	return 0;
301 }
302 
303 int board_eth_init(bd_t *bis)
304 {
305 	int rc = -ENODEV;
306 #if defined(CONFIG_SMC911X)
307 	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
308 #endif
309 
310 	cpu_eth_init(bis);
311 
312 	return rc;
313 }
314