1 /* 2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> 3 * 4 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <asm/io.h> 27 #include <asm/errno.h> 28 #include <asm/arch/imx-regs.h> 29 #include <asm/arch/crm_regs.h> 30 #include <asm/arch/mx35_pins.h> 31 #include <asm/arch/iomux.h> 32 #include <i2c.h> 33 #include <pmic.h> 34 #include <fsl_pmic.h> 35 #include <mmc.h> 36 #include <fsl_esdhc.h> 37 #include <mc9sdz60.h> 38 #include <mc13892.h> 39 #include <linux/types.h> 40 #include <asm/gpio.h> 41 #include <asm/arch/sys_proto.h> 42 #include <netdev.h> 43 44 #ifndef CONFIG_BOARD_LATE_INIT 45 #error "CONFIG_BOARD_LATE_INIT must be set for this board" 46 #endif 47 48 #ifndef CONFIG_BOARD_EARLY_INIT_F 49 #error "CONFIG_BOARD_EARLY_INIT_F must be set for this board" 50 #endif 51 52 DECLARE_GLOBAL_DATA_PTR; 53 54 int dram_init(void) 55 { 56 u32 size1, size2; 57 58 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 59 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); 60 61 gd->ram_size = size1 + size2; 62 63 return 0; 64 } 65 66 void dram_init_banksize(void) 67 { 68 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 69 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 70 71 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 72 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 73 } 74 75 static void setup_iomux_i2c(void) 76 { 77 int pad; 78 79 /* setup pins for I2C1 */ 80 mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION); 81 mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION); 82 83 pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \ 84 | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain); 85 86 mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad); 87 mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad); 88 } 89 90 91 static void setup_iomux_spi(void) 92 { 93 mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION); 94 mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION); 95 mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION); 96 mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION); 97 mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION); 98 } 99 100 static void setup_iomux_fec(void) 101 { 102 int pad; 103 104 /* setup pins for FEC */ 105 mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC); 106 mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC); 107 mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC); 108 mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC); 109 mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC); 110 mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC); 111 mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC); 112 mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC); 113 mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC); 114 mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC); 115 mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC); 116 mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC); 117 mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC); 118 mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC); 119 mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC); 120 mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC); 121 mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC); 122 mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC); 123 124 pad = (PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | \ 125 PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW); 126 127 mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \ 128 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 129 mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \ 130 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 131 mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, pad | PAD_CTL_HYS_SCHMITZ | \ 132 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 133 mxc_iomux_set_pad(MX35_PIN_FEC_COL, pad | PAD_CTL_HYS_SCHMITZ | \ 134 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 135 mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, pad | PAD_CTL_HYS_SCHMITZ | \ 136 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 137 mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, pad | PAD_CTL_HYS_CMOS | \ 138 PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); 139 mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, pad | PAD_CTL_HYS_CMOS | \ 140 PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); 141 mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad | PAD_CTL_HYS_CMOS | \ 142 PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); 143 mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad | PAD_CTL_HYS_SCHMITZ | \ 144 PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU); 145 mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, pad | PAD_CTL_HYS_CMOS | \ 146 PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); 147 mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, pad | PAD_CTL_HYS_SCHMITZ | \ 148 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 149 mxc_iomux_set_pad(MX35_PIN_FEC_CRS, pad | PAD_CTL_HYS_SCHMITZ | \ 150 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 151 mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, pad | PAD_CTL_HYS_SCHMITZ | \ 152 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 153 mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, pad | PAD_CTL_HYS_CMOS | \ 154 PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); 155 mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, pad | PAD_CTL_HYS_SCHMITZ | \ 156 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 157 mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, pad | PAD_CTL_HYS_CMOS | \ 158 PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); 159 mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, pad | PAD_CTL_HYS_SCHMITZ | \ 160 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); 161 mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, pad | PAD_CTL_HYS_CMOS | \ 162 PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); 163 } 164 165 int board_early_init_f(void) 166 { 167 struct ccm_regs *ccm = 168 (struct ccm_regs *)IMX_CCM_BASE; 169 170 /* enable clocks */ 171 writel(readl(&ccm->cgr0) | 172 MXC_CCM_CGR0_EMI_MASK | 173 MXC_CCM_CGR0_EDIO_MASK | 174 MXC_CCM_CGR0_EPIT1_MASK, 175 &ccm->cgr0); 176 177 writel(readl(&ccm->cgr1) | 178 MXC_CCM_CGR1_FEC_MASK | 179 MXC_CCM_CGR1_GPIO1_MASK | 180 MXC_CCM_CGR1_GPIO2_MASK | 181 MXC_CCM_CGR1_GPIO3_MASK | 182 MXC_CCM_CGR1_I2C1_MASK | 183 MXC_CCM_CGR1_I2C2_MASK | 184 MXC_CCM_CGR1_IPU_MASK, 185 &ccm->cgr1); 186 187 /* Setup NAND */ 188 __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); 189 190 setup_iomux_i2c(); 191 setup_iomux_fec(); 192 setup_iomux_spi(); 193 194 return 0; 195 } 196 197 int board_init(void) 198 { 199 gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */ 200 /* address of boot parameters */ 201 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 202 203 return 0; 204 } 205 206 static inline int pmic_detect(void) 207 { 208 unsigned int id; 209 struct pmic *p = get_pmic(); 210 211 pmic_reg_read(p, REG_IDENTIFICATION, &id); 212 213 id = (id >> 6) & 0x7; 214 if (id == 0x7) 215 return 1; 216 return 0; 217 } 218 219 u32 get_board_rev(void) 220 { 221 int rev; 222 223 rev = pmic_detect(); 224 225 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; 226 } 227 228 int board_late_init(void) 229 { 230 u8 val; 231 u32 pmic_val; 232 struct pmic *p; 233 234 pmic_init(); 235 if (pmic_detect()) { 236 p = get_pmic(); 237 mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION | 238 MUX_CONFIG_ALT1); 239 240 pmic_reg_read(p, REG_SETTING_0, &pmic_val); 241 pmic_reg_write(p, REG_SETTING_0, 242 pmic_val | VO_1_30V | VO_1_50V); 243 pmic_reg_read(p, REG_MODE_0, &pmic_val); 244 pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN); 245 246 mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO); 247 mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0); 248 249 gpio_direction_output(37, 1); 250 } 251 252 val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04; 253 mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val); 254 mdelay(200); 255 256 val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F; 257 mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val); 258 mdelay(200); 259 260 val |= 0x80; 261 mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val); 262 263 /* Print board revision */ 264 printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F); 265 266 return 0; 267 } 268 269 int board_eth_init(bd_t *bis) 270 { 271 int rc = -ENODEV; 272 #if defined(CONFIG_SMC911X) 273 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 274 #endif 275 276 cpu_eth_init(bis); 277 278 return rc; 279 } 280 281 #if defined(CONFIG_FSL_ESDHC) 282 283 struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR}; 284 285 int board_mmc_init(bd_t *bis) 286 { 287 /* configure pins for SDHC1 only */ 288 mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC); 289 mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC); 290 mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC); 291 mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC); 292 mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC); 293 mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC); 294 295 return fsl_esdhc_initialize(bis, &esdhc_cfg); 296 } 297 298 int board_mmc_getcd(struct mmc *mmc) 299 { 300 return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4); 301 } 302 #endif 303