1/*
2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
3 *
4 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22#include <config.h>
23#include <asm/arch/imx-regs.h>
24#include <generated/asm-offsets.h>
25#include "mx35pdk.h"
26#include <asm/arch/lowlevel_macro.S>
27
28/*
29 * return soc version
30 * 	0x10:  TO1
31 *	0x20:  TO2
32 *	0x30:  TO3
33 */
34.macro check_soc_version ret, tmp
35	ldr \tmp, =IIM_BASE_ADDR
36	ldr \ret, [\tmp, #IIM_SREV]
37	cmp \ret, #0x00
38	moveq \tmp, #ROMPATCH_REV
39	ldreq \ret, [\tmp]
40	moveq \ret, \ret, lsl #4
41	addne \ret, \ret, #0x10
42.endm
43
44/* CPLD on CS5 setup */
45.macro init_debug_board
46	ldr r0, =DBG_BASE_ADDR
47	ldr r1, =DBG_CSCR_U_CONFIG
48	str r1, [r0, #0x00]
49	ldr r1, =DBG_CSCR_L_CONFIG
50	str r1, [r0, #0x04]
51	ldr r1, =DBG_CSCR_A_CONFIG
52	str r1, [r0, #0x08]
53.endm
54
55/* clock setup */
56.macro init_clock
57	ldr r0, =CCM_BASE_ADDR
58
59	/* default CLKO to 1/32 of the ARM core*/
60	ldr r1, [r0, #CLKCTL_COSR]
61	bic r1, r1, #0x00000FF00
62	bic r1, r1, #0x0000000FF
63	mov r2, #0x00006C00
64	add r2, r2, #0x67
65	orr r1, r1, r2
66	str r1, [r0, #CLKCTL_COSR]
67
68	ldr r2, =CCM_CCMR_CONFIG
69	str r2, [r0, #CLKCTL_CCMR]
70
71	check_soc_version r1, r2
72	cmp r1, #CHIP_REV_2_0
73	ldrhs r3, =CCM_MPLL_532_HZ
74	bhs 1f
75	ldr r2, [r0, #CLKCTL_PDR0]
76	tst r2, #CLKMODE_CONSUMER
77	ldrne r3, =CCM_MPLL_532_HZ  /* consumer path*/
78	ldreq r3, =CCM_MPLL_399_HZ  /* auto path*/
791:
80	str r3, [r0, #CLKCTL_MPCTL]
81
82	ldr r1, =CCM_PPLL_300_HZ
83	str r1, [r0, #CLKCTL_PPCTL]
84
85	ldr r1, =CCM_PDR0_CONFIG
86	bic r1, r1, #0x800000
87	str r1, [r0, #CLKCTL_PDR0]
88
89	ldr r1, [r0, #CLKCTL_CGR0]
90	orr r1, r1, #0x0C300000
91	str r1, [r0, #CLKCTL_CGR0]
92
93	ldr r1, [r0, #CLKCTL_CGR1]
94	orr r1, r1, #0x00000C00
95	orr r1, r1, #0x00000003
96	str r1, [r0, #CLKCTL_CGR1]
97.endm
98
99.macro setup_sdram
100	ldr r0, =ESDCTL_BASE_ADDR
101	mov r3, #0x2000
102	str r3, [r0, #0x0]
103	str r3, [r0, #0x8]
104
105	/*ip(r12) has used to save lr register in upper calling*/
106	mov fp, lr
107
108	mov r5, #0x00
109	mov r2, #0x00
110	mov r1, #CSD0_BASE_ADDR
111	bl setup_sdram_bank
112
113	mov r5, #0x00
114	mov r2, #0x00
115	mov r1, #CSD1_BASE_ADDR
116	bl setup_sdram_bank
117
118	mov lr, fp
119
1201:
121	ldr r3, =ESDCTL_DELAY_LINE5
122	str r3, [r0, #0x30]
123.endm
124
125.globl lowlevel_init
126lowlevel_init:
127	mov r10, lr
128
129	core_init
130
131	init_aips
132
133	init_max
134
135	init_m3if
136
137	init_clock
138	init_debug_board
139
140	cmp pc, #PHYS_SDRAM_1
141	blo init_sdram_start
142	cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
143	blo skip_sdram_setup
144
145init_sdram_start:
146	/*init_sdram*/
147	setup_sdram
148
149skip_sdram_setup:
150	mov lr, r10
151	mov pc, lr
152
153
154/*
155 * r0: ESDCTL control base, r1: sdram slot base
156 * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
157 */
158setup_sdram_bank:
159	mov r3, #0xE
160	tst r2, #0x1
161	orreq r3, r3, #0x300 /*DDR2*/
162	str r3, [r0, #0x10]
163	bic r3, r3, #0x00A
164	str r3, [r0, #0x10]
165	beq 2f
166
167	mov r3, #0x20000
1681:      subs r3, r3, #1
169	bne 1b
170
1712:      tst r2, #0x1
172	ldreq r3, =ESDCTL_DDR2_CONFIG
173	ldrne r3, =ESDCTL_MDDR_CONFIG
174	cmp r1, #CSD1_BASE_ADDR
175	strlo r3, [r0, #0x4]
176	strhs r3, [r0, #0xC]
177
178	ldr r3, =ESDCTL_0x92220000
179	strlo r3, [r0, #0x0]
180	strhs r3, [r0, #0x8]
181	mov r3, #0xDA
182	ldr r4, =ESDCTL_PRECHARGE
183	strb r3, [r1, r4]
184
185	tst r2, #0x1
186	bne skip_set_mode
187
188	cmp r1, #CSD1_BASE_ADDR
189	ldr r3, =ESDCTL_0xB2220000
190	strlo r3, [r0, #0x0]
191	strhs r3, [r0, #0x8]
192	mov r3, #0xDA
193	ldr r4, =ESDCTL_DDR2_EMR2
194	strb r3, [r1, r4]
195	ldr r4, =ESDCTL_DDR2_EMR3
196	strb r3, [r1, r4]
197	ldr r4, =ESDCTL_DDR2_EN_DLL
198	strb r3, [r1, r4]
199	ldr r4, =ESDCTL_DDR2_RESET_DLL
200	strb r3, [r1, r4]
201
202	ldr r3, =ESDCTL_0x92220000
203	strlo r3, [r0, #0x0]
204	strhs r3, [r0, #0x8]
205	mov r3, #0xDA
206	ldr r4, =ESDCTL_PRECHARGE
207	strb r3, [r1, r4]
208
209skip_set_mode:
210	cmp r1, #CSD1_BASE_ADDR
211	ldr r3, =ESDCTL_0xA2220000
212	strlo r3, [r0, #0x0]
213	strhs r3, [r0, #0x8]
214	mov r3, #0xDA
215	strb r3, [r1]
216	strb r3, [r1]
217
218	ldr r3, =ESDCTL_0xB2220000
219	strlo r3, [r0, #0x0]
220	strhs r3, [r0, #0x8]
221	tst r2, #0x1
222	ldreq r4, =ESDCTL_DDR2_MR
223	ldrne r4, =ESDCTL_MDDR_MR
224	mov r3, #0xDA
225	strb r3, [r1, r4]
226	ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
227	streqb r3, [r1, r4]
228	ldreq r4, =ESDCTL_DDR2_EN_DLL
229	ldrne r4, =ESDCTL_MDDR_EMR
230	strb r3, [r1, r4]
231
232	cmp r1, #CSD1_BASE_ADDR
233	ldr r3, =ESDCTL_0x82228080
234	strlo r3, [r0, #0x0]
235	strhs r3, [r0, #0x8]
236
237	tst r2, #0x1
238	moveq r4, #0x20000
239	movne r4, #0x200
2401:      subs r4, r4, #1
241	bne 1b
242
243	str r3, [r1, #0x100]
244	ldr r4, [r1, #0x100]
245	cmp r3, r4
246	movne r3, #1
247	moveq r3, #0
248
249	mov pc, lr
250