1 /*
2  *
3  * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
4  *
5  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6  *
7  * See file CREDITS for list of people who contributed to this
8  * project.
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License as
12  * published by the Free Software Foundation; either version 2 of
13  * the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23  * MA 02111-1307 USA
24  */
25 
26 
27 #include <common.h>
28 #include <netdev.h>
29 #include <asm/arch/clock.h>
30 #include <asm/arch/imx-regs.h>
31 #include <asm/arch/sys_proto.h>
32 #include <watchdog.h>
33 #include <pmic.h>
34 #include <fsl_pmic.h>
35 
36 DECLARE_GLOBAL_DATA_PTR;
37 
38 #ifdef CONFIG_HW_WATCHDOG
39 void hw_watchdog_reset(void)
40 {
41 	mxc_hw_watchdog_reset();
42 }
43 #endif
44 
45 int dram_init(void)
46 {
47 	/* dram_init must store complete ramsize in gd->ram_size */
48 	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
49 				PHYS_SDRAM_1_SIZE);
50 	return 0;
51 }
52 
53 int board_early_init_f(void)
54 {
55 	/* CS5: CPLD incl. network controller */
56 	static const struct mxc_weimcs cs5 = {
57 		/*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
58 		CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  3, 24, 0,  4,  3),
59 		/*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
60 		CSCR_L(2,  2,   2,   5,  2,  0,  5,  2,  0,  0,   0,   1),
61 		/*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
62 		CSCR_A(2,   2,  2,  2,  0,  0,  2,  2,  0,  0,  0,  0,   0,  0)
63 	};
64 
65 	mxc_setup_weimcs(5, &cs5);
66 
67 	/* Setup UART1 and SPI2 pins */
68 	mx31_uart1_hw_init();
69 	mx31_spi2_hw_init();
70 
71 	return 0;
72 }
73 
74 void enable_caches(void)
75 {
76 	icache_enable();
77 	dcache_enable();
78 }
79 
80 int board_init(void)
81 {
82 	/* adress of boot parameters */
83 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
84 
85 	enable_caches();
86 
87 	return 0;
88 }
89 
90 int board_late_init(void)
91 {
92 	u32 val;
93 	struct pmic *p;
94 
95 	pmic_init();
96 	p = get_pmic();
97 
98 	/* Enable RTC battery */
99 	pmic_reg_read(p, REG_POWER_CTL0, &val);
100 	pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
101 	pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
102 #ifdef CONFIG_HW_WATCHDOG
103 	mxc_hw_watchdog_enable();
104 #endif
105 	return 0;
106 }
107 
108 int checkboard(void)
109 {
110 	printf("Board: MX31PDK\n");
111 	return 0;
112 }
113 
114 int board_eth_init(bd_t *bis)
115 {
116 	int rc = 0;
117 #ifdef CONFIG_SMC911X
118 	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
119 #endif
120 	return rc;
121 }
122