1 /* 2 * Freescale MX28EVK board 3 * 4 * (C) Copyright 2011 Freescale Semiconductor, Inc. 5 * 6 * Author: Fabio Estevam <fabio.estevam@freescale.com> 7 * 8 * Based on m28evk.c: 9 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 10 * on behalf of DENX Software Engineering GmbH 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 */ 25 26 #include <common.h> 27 #include <asm/gpio.h> 28 #include <asm/io.h> 29 #include <asm/arch/imx-regs.h> 30 #include <asm/arch/iomux-mx28.h> 31 #include <asm/arch/clock.h> 32 #include <asm/arch/sys_proto.h> 33 #include <linux/mii.h> 34 #include <miiphy.h> 35 #include <netdev.h> 36 #include <errno.h> 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 /* 41 * Functions 42 */ 43 int board_early_init_f(void) 44 { 45 /* IO0 clock at 480MHz */ 46 mx28_set_ioclk(MXC_IOCLK0, 480000); 47 /* IO1 clock at 480MHz */ 48 mx28_set_ioclk(MXC_IOCLK1, 480000); 49 50 /* SSP0 clock at 96MHz */ 51 mx28_set_sspclk(MXC_SSPCLK0, 96000, 0); 52 /* SSP2 clock at 96MHz */ 53 mx28_set_sspclk(MXC_SSPCLK2, 96000, 0); 54 55 #ifdef CONFIG_CMD_USB 56 mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT); 57 mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 | 58 MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL); 59 gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1); 60 #endif 61 62 return 0; 63 } 64 65 int dram_init(void) 66 { 67 return mxs_dram_init(); 68 } 69 70 int board_init(void) 71 { 72 /* Adress of boot parameters */ 73 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 74 75 return 0; 76 } 77 78 #ifdef CONFIG_CMD_MMC 79 static int mx28evk_mmc_wp(int id) 80 { 81 if (id != 0) { 82 printf("MXS MMC: Invalid card selected (card id = %d)\n", id); 83 return 1; 84 } 85 86 return gpio_get_value(MX28_PAD_SSP1_SCK__GPIO_2_12); 87 } 88 89 int board_mmc_init(bd_t *bis) 90 { 91 /* Configure WP as input */ 92 gpio_direction_input(MX28_PAD_SSP1_SCK__GPIO_2_12); 93 94 /* Configure MMC0 Power Enable */ 95 gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0); 96 97 return mxsmmc_initialize(bis, 0, mx28evk_mmc_wp); 98 } 99 #endif 100 101 #ifdef CONFIG_CMD_NET 102 103 #define MII_OPMODE_STRAP_OVERRIDE 0x16 104 #define MII_PHY_CTRL1 0x1e 105 #define MII_PHY_CTRL2 0x1f 106 107 int fecmxc_mii_postcall(int phy) 108 { 109 miiphy_write("FEC1", phy, MII_BMCR, 0x9000); 110 miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202); 111 if (phy == 3) 112 miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180); 113 return 0; 114 } 115 116 int board_eth_init(bd_t *bis) 117 { 118 struct mxs_clkctrl_regs *clkctrl_regs = 119 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 120 struct eth_device *dev; 121 int ret; 122 123 ret = cpu_eth_init(bis); 124 125 /* MX28EVK uses ENET_CLK PAD to drive FEC clock */ 126 writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, 127 &clkctrl_regs->hw_clkctrl_enet); 128 129 /* Power-on FECs */ 130 gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0); 131 132 /* Reset FEC PHYs */ 133 gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0); 134 udelay(200); 135 gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1); 136 137 ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); 138 if (ret) { 139 puts("FEC MXS: Unable to init FEC0\n"); 140 return ret; 141 } 142 143 ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE); 144 if (ret) { 145 puts("FEC MXS: Unable to init FEC1\n"); 146 return ret; 147 } 148 149 dev = eth_get_dev_by_name("FEC0"); 150 if (!dev) { 151 puts("FEC MXS: Unable to get FEC0 device entry\n"); 152 return -EINVAL; 153 } 154 155 ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); 156 if (ret) { 157 puts("FEC MXS: Unable to register FEC0 mii postcall\n"); 158 return ret; 159 } 160 161 dev = eth_get_dev_by_name("FEC1"); 162 if (!dev) { 163 puts("FEC MXS: Unable to get FEC1 device entry\n"); 164 return -EINVAL; 165 } 166 167 ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); 168 if (ret) { 169 puts("FEC MXS: Unable to register FEC1 mii postcall\n"); 170 return ret; 171 } 172 173 return ret; 174 } 175 176 #endif 177