129f75a5cSFabio Estevam /* 229f75a5cSFabio Estevam * Freescale MX28EVK IOMUX setup 329f75a5cSFabio Estevam * 429f75a5cSFabio Estevam * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 529f75a5cSFabio Estevam * on behalf of DENX Software Engineering GmbH 629f75a5cSFabio Estevam * 729f75a5cSFabio Estevam * See file CREDITS for list of people who contributed to this 829f75a5cSFabio Estevam * project. 929f75a5cSFabio Estevam * 1029f75a5cSFabio Estevam * This program is free software; you can redistribute it and/or 1129f75a5cSFabio Estevam * modify it under the terms of the GNU General Public License as 1229f75a5cSFabio Estevam * published by the Free Software Foundation; either version 2 of 1329f75a5cSFabio Estevam * the License, or (at your option) any later version. 1429f75a5cSFabio Estevam * 1529f75a5cSFabio Estevam * This program is distributed in the hope that it will be useful, 1629f75a5cSFabio Estevam * but WITHOUT ANY WARRANTY; without even the implied warranty of 1729f75a5cSFabio Estevam * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1829f75a5cSFabio Estevam * GNU General Public License for more details. 1929f75a5cSFabio Estevam */ 2029f75a5cSFabio Estevam 2129f75a5cSFabio Estevam #include <common.h> 2229f75a5cSFabio Estevam #include <config.h> 2329f75a5cSFabio Estevam #include <asm/io.h> 2429f75a5cSFabio Estevam #include <asm/arch/iomux-mx28.h> 2529f75a5cSFabio Estevam #include <asm/arch/imx-regs.h> 2629f75a5cSFabio Estevam #include <asm/arch/sys_proto.h> 2729f75a5cSFabio Estevam 2829f75a5cSFabio Estevam #define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) 29ecb7be29SLauri Hintsala #define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) 3029f75a5cSFabio Estevam #define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) 3129f75a5cSFabio Estevam #define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) 32ed97abedSMatthias Fuchs #define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) 3329f75a5cSFabio Estevam 3429f75a5cSFabio Estevam const iomux_cfg_t iomux_setup[] = { 3529f75a5cSFabio Estevam /* DUART */ 3629f75a5cSFabio Estevam MX28_PAD_PWM0__DUART_RX, 3729f75a5cSFabio Estevam MX28_PAD_PWM1__DUART_TX, 3829f75a5cSFabio Estevam 3929f75a5cSFabio Estevam /* MMC0 */ 4029f75a5cSFabio Estevam MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, 4129f75a5cSFabio Estevam MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, 4229f75a5cSFabio Estevam MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, 4329f75a5cSFabio Estevam MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, 4429f75a5cSFabio Estevam MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0, 4529f75a5cSFabio Estevam MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0, 4629f75a5cSFabio Estevam MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0, 4729f75a5cSFabio Estevam MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0, 4829f75a5cSFabio Estevam MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, 4929f75a5cSFabio Estevam MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | 5029f75a5cSFabio Estevam (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), 5129f75a5cSFabio Estevam MX28_PAD_SSP0_SCK__SSP0_SCK | 5229f75a5cSFabio Estevam (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), 5329f75a5cSFabio Estevam /* write protect */ 5429f75a5cSFabio Estevam MX28_PAD_SSP1_SCK__GPIO_2_12, 5529f75a5cSFabio Estevam /* MMC0 slot power enable */ 5629f75a5cSFabio Estevam MX28_PAD_PWM3__GPIO_3_28 | 5729f75a5cSFabio Estevam (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 5829f75a5cSFabio Estevam 59ecb7be29SLauri Hintsala #ifdef CONFIG_NAND_MXS 60ecb7be29SLauri Hintsala /* GPMI NAND */ 61ecb7be29SLauri Hintsala MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, 62ecb7be29SLauri Hintsala MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, 63ecb7be29SLauri Hintsala MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, 64ecb7be29SLauri Hintsala MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, 65ecb7be29SLauri Hintsala MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, 66ecb7be29SLauri Hintsala MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, 67ecb7be29SLauri Hintsala MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, 68ecb7be29SLauri Hintsala MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, 69ecb7be29SLauri Hintsala MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, 70ecb7be29SLauri Hintsala MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, 71ecb7be29SLauri Hintsala MX28_PAD_GPMI_RDN__GPMI_RDN | 72ecb7be29SLauri Hintsala (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), 73ecb7be29SLauri Hintsala MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, 74ecb7be29SLauri Hintsala MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, 75ecb7be29SLauri Hintsala MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, 76ecb7be29SLauri Hintsala MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, 77ecb7be29SLauri Hintsala #endif 78ecb7be29SLauri Hintsala 7929f75a5cSFabio Estevam /* FEC0 */ 8029f75a5cSFabio Estevam MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, 8129f75a5cSFabio Estevam MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, 8229f75a5cSFabio Estevam MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, 8329f75a5cSFabio Estevam MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, 8429f75a5cSFabio Estevam MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, 8529f75a5cSFabio Estevam MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, 8629f75a5cSFabio Estevam MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, 8729f75a5cSFabio Estevam MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, 8829f75a5cSFabio Estevam MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, 8929f75a5cSFabio Estevam /* FEC0 Enable */ 9029f75a5cSFabio Estevam MX28_PAD_SSP1_DATA3__GPIO_2_15 | 9129f75a5cSFabio Estevam (MXS_PAD_12MA | MXS_PAD_3V3), 9229f75a5cSFabio Estevam /* FEC0 Reset */ 9329f75a5cSFabio Estevam MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | 9429f75a5cSFabio Estevam (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 9529f75a5cSFabio Estevam 9629f75a5cSFabio Estevam /* FEC1 */ 9729f75a5cSFabio Estevam MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET, 9829f75a5cSFabio Estevam MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET, 9929f75a5cSFabio Estevam MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET, 10029f75a5cSFabio Estevam MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET, 10129f75a5cSFabio Estevam MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET, 10229f75a5cSFabio Estevam MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET, 10329f75a5cSFabio Estevam 10429f75a5cSFabio Estevam /* EMI */ 10529f75a5cSFabio Estevam MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, 10629f75a5cSFabio Estevam MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, 10729f75a5cSFabio Estevam MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, 10829f75a5cSFabio Estevam MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, 10929f75a5cSFabio Estevam MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, 11029f75a5cSFabio Estevam MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, 11129f75a5cSFabio Estevam MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, 11229f75a5cSFabio Estevam MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, 11329f75a5cSFabio Estevam MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, 11429f75a5cSFabio Estevam MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, 11529f75a5cSFabio Estevam MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, 11629f75a5cSFabio Estevam MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, 11729f75a5cSFabio Estevam MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, 11829f75a5cSFabio Estevam MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, 11929f75a5cSFabio Estevam MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, 12029f75a5cSFabio Estevam MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, 12129f75a5cSFabio Estevam MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, 12229f75a5cSFabio Estevam MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, 12329f75a5cSFabio Estevam MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, 12429f75a5cSFabio Estevam MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, 12529f75a5cSFabio Estevam MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, 12629f75a5cSFabio Estevam MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, 12729f75a5cSFabio Estevam MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, 12829f75a5cSFabio Estevam MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, 12929f75a5cSFabio Estevam MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, 13029f75a5cSFabio Estevam 13129f75a5cSFabio Estevam MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, 13229f75a5cSFabio Estevam MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, 13329f75a5cSFabio Estevam MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, 13429f75a5cSFabio Estevam MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, 13529f75a5cSFabio Estevam MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, 13629f75a5cSFabio Estevam MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, 13729f75a5cSFabio Estevam MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, 13829f75a5cSFabio Estevam MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, 13929f75a5cSFabio Estevam MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, 14029f75a5cSFabio Estevam MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, 14129f75a5cSFabio Estevam MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, 14229f75a5cSFabio Estevam MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, 14329f75a5cSFabio Estevam MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, 14429f75a5cSFabio Estevam MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, 14529f75a5cSFabio Estevam MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, 14629f75a5cSFabio Estevam MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, 14729f75a5cSFabio Estevam MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, 14829f75a5cSFabio Estevam MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, 14929f75a5cSFabio Estevam MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, 15029f75a5cSFabio Estevam MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, 15129f75a5cSFabio Estevam MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, 15229f75a5cSFabio Estevam MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, 15329f75a5cSFabio Estevam MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, 15429f75a5cSFabio Estevam MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, 155ed97abedSMatthias Fuchs 156ed97abedSMatthias Fuchs /* SPI2 (for SPI flash) */ 157ed97abedSMatthias Fuchs MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2, 158ed97abedSMatthias Fuchs MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2, 159ed97abedSMatthias Fuchs MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2, 160ed97abedSMatthias Fuchs MX28_PAD_SSP2_SS0__SSP2_D3 | 161ed97abedSMatthias Fuchs (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), 16229f75a5cSFabio Estevam }; 16329f75a5cSFabio Estevam 164*f69b0653SFabio Estevam #define HW_DRAM_CTL29 (0x74 >> 2) 165*f69b0653SFabio Estevam #define CS_MAP 0xf 166*f69b0653SFabio Estevam #define COLUMN_SIZE 0x2 167*f69b0653SFabio Estevam #define ADDR_PINS 0x1 168*f69b0653SFabio Estevam #define APREBIT 0xa 169*f69b0653SFabio Estevam 170*f69b0653SFabio Estevam #define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \ 171*f69b0653SFabio Estevam ADDR_PINS << 8 | APREBIT) 172*f69b0653SFabio Estevam 173*f69b0653SFabio Estevam void mx28_adjust_memory_params(uint32_t *dram_vals) 174*f69b0653SFabio Estevam { 175*f69b0653SFabio Estevam dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG; 176*f69b0653SFabio Estevam } 177*f69b0653SFabio Estevam 17829f75a5cSFabio Estevam void board_init_ll(void) 17929f75a5cSFabio Estevam { 18029f75a5cSFabio Estevam mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); 18129f75a5cSFabio Estevam } 182