1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 229f75a5cSFabio Estevam /* 329f75a5cSFabio Estevam * Freescale MX28EVK IOMUX setup 429f75a5cSFabio Estevam * 529f75a5cSFabio Estevam * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 629f75a5cSFabio Estevam * on behalf of DENX Software Engineering GmbH 729f75a5cSFabio Estevam */ 829f75a5cSFabio Estevam 929f75a5cSFabio Estevam #include <common.h> 1029f75a5cSFabio Estevam #include <config.h> 1129f75a5cSFabio Estevam #include <asm/io.h> 1229f75a5cSFabio Estevam #include <asm/arch/iomux-mx28.h> 1329f75a5cSFabio Estevam #include <asm/arch/imx-regs.h> 1429f75a5cSFabio Estevam #include <asm/arch/sys_proto.h> 1529f75a5cSFabio Estevam 1629f75a5cSFabio Estevam #define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) 17ecb7be29SLauri Hintsala #define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) 1829f75a5cSFabio Estevam #define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) 1929f75a5cSFabio Estevam #define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) 20ed97abedSMatthias Fuchs #define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) 2168661db2SFabio Estevam #define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) 2229f75a5cSFabio Estevam 2329f75a5cSFabio Estevam const iomux_cfg_t iomux_setup[] = { 2429f75a5cSFabio Estevam /* DUART */ 2529f75a5cSFabio Estevam MX28_PAD_PWM0__DUART_RX, 2629f75a5cSFabio Estevam MX28_PAD_PWM1__DUART_TX, 2729f75a5cSFabio Estevam 2829f75a5cSFabio Estevam /* MMC0 */ 2929f75a5cSFabio Estevam MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, 3029f75a5cSFabio Estevam MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, 3129f75a5cSFabio Estevam MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, 3229f75a5cSFabio Estevam MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, 3329f75a5cSFabio Estevam MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0, 3429f75a5cSFabio Estevam MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0, 3529f75a5cSFabio Estevam MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0, 3629f75a5cSFabio Estevam MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0, 3729f75a5cSFabio Estevam MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, 3829f75a5cSFabio Estevam MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | 3929f75a5cSFabio Estevam (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), 4029f75a5cSFabio Estevam MX28_PAD_SSP0_SCK__SSP0_SCK | 4129f75a5cSFabio Estevam (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), 4229f75a5cSFabio Estevam /* write protect */ 4329f75a5cSFabio Estevam MX28_PAD_SSP1_SCK__GPIO_2_12, 4429f75a5cSFabio Estevam /* MMC0 slot power enable */ 4529f75a5cSFabio Estevam MX28_PAD_PWM3__GPIO_3_28 | 4629f75a5cSFabio Estevam (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 4729f75a5cSFabio Estevam 48ecb7be29SLauri Hintsala #ifdef CONFIG_NAND_MXS 49ecb7be29SLauri Hintsala /* GPMI NAND */ 50ecb7be29SLauri Hintsala MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, 51ecb7be29SLauri Hintsala MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, 52ecb7be29SLauri Hintsala MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, 53ecb7be29SLauri Hintsala MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, 54ecb7be29SLauri Hintsala MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, 55ecb7be29SLauri Hintsala MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, 56ecb7be29SLauri Hintsala MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, 57ecb7be29SLauri Hintsala MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, 58ecb7be29SLauri Hintsala MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, 59ecb7be29SLauri Hintsala MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, 60ecb7be29SLauri Hintsala MX28_PAD_GPMI_RDN__GPMI_RDN | 61ecb7be29SLauri Hintsala (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), 62ecb7be29SLauri Hintsala MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, 63ecb7be29SLauri Hintsala MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, 64ecb7be29SLauri Hintsala MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, 65ecb7be29SLauri Hintsala MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, 66ecb7be29SLauri Hintsala #endif 67ecb7be29SLauri Hintsala 6829f75a5cSFabio Estevam /* FEC0 */ 6929f75a5cSFabio Estevam MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, 7029f75a5cSFabio Estevam MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, 7129f75a5cSFabio Estevam MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, 7229f75a5cSFabio Estevam MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, 7329f75a5cSFabio Estevam MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, 7429f75a5cSFabio Estevam MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, 7529f75a5cSFabio Estevam MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, 7629f75a5cSFabio Estevam MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, 7729f75a5cSFabio Estevam MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, 7829f75a5cSFabio Estevam /* FEC0 Enable */ 7929f75a5cSFabio Estevam MX28_PAD_SSP1_DATA3__GPIO_2_15 | 8029f75a5cSFabio Estevam (MXS_PAD_12MA | MXS_PAD_3V3), 8129f75a5cSFabio Estevam /* FEC0 Reset */ 8229f75a5cSFabio Estevam MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | 8329f75a5cSFabio Estevam (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 8429f75a5cSFabio Estevam 8529f75a5cSFabio Estevam /* FEC1 */ 8629f75a5cSFabio Estevam MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET, 8729f75a5cSFabio Estevam MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET, 8829f75a5cSFabio Estevam MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET, 8929f75a5cSFabio Estevam MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET, 9029f75a5cSFabio Estevam MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET, 9129f75a5cSFabio Estevam MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET, 9229f75a5cSFabio Estevam 9329f75a5cSFabio Estevam /* EMI */ 9429f75a5cSFabio Estevam MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, 9529f75a5cSFabio Estevam MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, 9629f75a5cSFabio Estevam MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, 9729f75a5cSFabio Estevam MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, 9829f75a5cSFabio Estevam MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, 9929f75a5cSFabio Estevam MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, 10029f75a5cSFabio Estevam MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, 10129f75a5cSFabio Estevam MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, 10229f75a5cSFabio Estevam MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, 10329f75a5cSFabio Estevam MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, 10429f75a5cSFabio Estevam MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, 10529f75a5cSFabio Estevam MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, 10629f75a5cSFabio Estevam MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, 10729f75a5cSFabio Estevam MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, 10829f75a5cSFabio Estevam MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, 10929f75a5cSFabio Estevam MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, 11029f75a5cSFabio Estevam MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, 11129f75a5cSFabio Estevam MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, 11229f75a5cSFabio Estevam MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, 11329f75a5cSFabio Estevam MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, 11429f75a5cSFabio Estevam MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, 11529f75a5cSFabio Estevam MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, 11629f75a5cSFabio Estevam MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, 11729f75a5cSFabio Estevam MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, 11829f75a5cSFabio Estevam MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, 11929f75a5cSFabio Estevam 12029f75a5cSFabio Estevam MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, 12129f75a5cSFabio Estevam MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, 12229f75a5cSFabio Estevam MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, 12329f75a5cSFabio Estevam MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, 12429f75a5cSFabio Estevam MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, 12529f75a5cSFabio Estevam MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, 12629f75a5cSFabio Estevam MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, 12729f75a5cSFabio Estevam MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, 12829f75a5cSFabio Estevam MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, 12929f75a5cSFabio Estevam MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, 13029f75a5cSFabio Estevam MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, 13129f75a5cSFabio Estevam MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, 13229f75a5cSFabio Estevam MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, 13329f75a5cSFabio Estevam MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, 13429f75a5cSFabio Estevam MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, 13529f75a5cSFabio Estevam MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, 13629f75a5cSFabio Estevam MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, 13729f75a5cSFabio Estevam MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, 13829f75a5cSFabio Estevam MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, 13929f75a5cSFabio Estevam MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, 14029f75a5cSFabio Estevam MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, 14129f75a5cSFabio Estevam MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, 14229f75a5cSFabio Estevam MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, 14329f75a5cSFabio Estevam MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, 144ed97abedSMatthias Fuchs 145ed97abedSMatthias Fuchs /* SPI2 (for SPI flash) */ 146ed97abedSMatthias Fuchs MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2, 147ed97abedSMatthias Fuchs MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2, 148ed97abedSMatthias Fuchs MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2, 149ed97abedSMatthias Fuchs MX28_PAD_SSP2_SS0__SSP2_D3 | 150ed97abedSMatthias Fuchs (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), 151175a7d27SFabio Estevam /* I2C */ 152175a7d27SFabio Estevam MX28_PAD_I2C0_SCL__I2C0_SCL, 153175a7d27SFabio Estevam MX28_PAD_I2C0_SDA__I2C0_SDA, 15468661db2SFabio Estevam 15568661db2SFabio Estevam /* LCD */ 15668661db2SFabio Estevam MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD, 15768661db2SFabio Estevam MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD, 15868661db2SFabio Estevam MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD, 15968661db2SFabio Estevam MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD, 16068661db2SFabio Estevam MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD, 16168661db2SFabio Estevam MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD, 16268661db2SFabio Estevam MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD, 16368661db2SFabio Estevam MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD, 16468661db2SFabio Estevam MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD, 16568661db2SFabio Estevam MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD, 16668661db2SFabio Estevam MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, 16768661db2SFabio Estevam MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, 16868661db2SFabio Estevam MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, 16968661db2SFabio Estevam MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, 17068661db2SFabio Estevam MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, 17168661db2SFabio Estevam MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, 17268661db2SFabio Estevam MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, 17368661db2SFabio Estevam MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, 17468661db2SFabio Estevam MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD, 17568661db2SFabio Estevam MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD, 17668661db2SFabio Estevam MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD, 17768661db2SFabio Estevam MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD, 17868661db2SFabio Estevam MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD, 17968661db2SFabio Estevam MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD, 18068661db2SFabio Estevam MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD, 18168661db2SFabio Estevam MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD, 18268661db2SFabio Estevam MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD, 18368661db2SFabio Estevam MX28_PAD_LCD_CS__LCD_ENABLE | MUX_CONFIG_LCD, 18468661db2SFabio Estevam MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD, /* LCD power */ 18568661db2SFabio Estevam MX28_PAD_PWM2__GPIO_3_18 | MUX_CONFIG_LCD, /* LCD contrast */ 18629f75a5cSFabio Estevam }; 18729f75a5cSFabio Estevam 188f69b0653SFabio Estevam #define HW_DRAM_CTL29 (0x74 >> 2) 189f69b0653SFabio Estevam #define CS_MAP 0xf 190f69b0653SFabio Estevam #define COLUMN_SIZE 0x2 191f69b0653SFabio Estevam #define ADDR_PINS 0x1 192f69b0653SFabio Estevam #define APREBIT 0xa 193f69b0653SFabio Estevam 194f69b0653SFabio Estevam #define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \ 195f69b0653SFabio Estevam ADDR_PINS << 8 | APREBIT) 196f69b0653SFabio Estevam 197ddfcc810SFabio Estevam void mxs_adjust_memory_params(uint32_t *dram_vals) 198f69b0653SFabio Estevam { 199f69b0653SFabio Estevam dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG; 200f69b0653SFabio Estevam } 201f69b0653SFabio Estevam 2027b8657e2SMarek Vasut void board_init_ll(const uint32_t arg, const uint32_t *resptr) 20329f75a5cSFabio Estevam { 2047b8657e2SMarek Vasut mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); 20529f75a5cSFabio Estevam } 206