1*29f75a5cSFabio Estevam /* 2*29f75a5cSFabio Estevam * Freescale MX28EVK IOMUX setup 3*29f75a5cSFabio Estevam * 4*29f75a5cSFabio Estevam * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5*29f75a5cSFabio Estevam * on behalf of DENX Software Engineering GmbH 6*29f75a5cSFabio Estevam * 7*29f75a5cSFabio Estevam * See file CREDITS for list of people who contributed to this 8*29f75a5cSFabio Estevam * project. 9*29f75a5cSFabio Estevam * 10*29f75a5cSFabio Estevam * This program is free software; you can redistribute it and/or 11*29f75a5cSFabio Estevam * modify it under the terms of the GNU General Public License as 12*29f75a5cSFabio Estevam * published by the Free Software Foundation; either version 2 of 13*29f75a5cSFabio Estevam * the License, or (at your option) any later version. 14*29f75a5cSFabio Estevam * 15*29f75a5cSFabio Estevam * This program is distributed in the hope that it will be useful, 16*29f75a5cSFabio Estevam * but WITHOUT ANY WARRANTY; without even the implied warranty of 17*29f75a5cSFabio Estevam * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18*29f75a5cSFabio Estevam * GNU General Public License for more details. 19*29f75a5cSFabio Estevam */ 20*29f75a5cSFabio Estevam 21*29f75a5cSFabio Estevam #include <common.h> 22*29f75a5cSFabio Estevam #include <config.h> 23*29f75a5cSFabio Estevam #include <asm/io.h> 24*29f75a5cSFabio Estevam #include <asm/arch/iomux-mx28.h> 25*29f75a5cSFabio Estevam #include <asm/arch/imx-regs.h> 26*29f75a5cSFabio Estevam #include <asm/arch/sys_proto.h> 27*29f75a5cSFabio Estevam 28*29f75a5cSFabio Estevam #define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) 29*29f75a5cSFabio Estevam #define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) 30*29f75a5cSFabio Estevam #define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) 31*29f75a5cSFabio Estevam 32*29f75a5cSFabio Estevam const iomux_cfg_t iomux_setup[] = { 33*29f75a5cSFabio Estevam /* DUART */ 34*29f75a5cSFabio Estevam MX28_PAD_PWM0__DUART_RX, 35*29f75a5cSFabio Estevam MX28_PAD_PWM1__DUART_TX, 36*29f75a5cSFabio Estevam 37*29f75a5cSFabio Estevam /* MMC0 */ 38*29f75a5cSFabio Estevam MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, 39*29f75a5cSFabio Estevam MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, 40*29f75a5cSFabio Estevam MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, 41*29f75a5cSFabio Estevam MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, 42*29f75a5cSFabio Estevam MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0, 43*29f75a5cSFabio Estevam MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0, 44*29f75a5cSFabio Estevam MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0, 45*29f75a5cSFabio Estevam MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0, 46*29f75a5cSFabio Estevam MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, 47*29f75a5cSFabio Estevam MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | 48*29f75a5cSFabio Estevam (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), 49*29f75a5cSFabio Estevam MX28_PAD_SSP0_SCK__SSP0_SCK | 50*29f75a5cSFabio Estevam (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), 51*29f75a5cSFabio Estevam /* write protect */ 52*29f75a5cSFabio Estevam MX28_PAD_SSP1_SCK__GPIO_2_12, 53*29f75a5cSFabio Estevam /* MMC0 slot power enable */ 54*29f75a5cSFabio Estevam MX28_PAD_PWM3__GPIO_3_28 | 55*29f75a5cSFabio Estevam (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 56*29f75a5cSFabio Estevam 57*29f75a5cSFabio Estevam /* FEC0 */ 58*29f75a5cSFabio Estevam MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, 59*29f75a5cSFabio Estevam MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, 60*29f75a5cSFabio Estevam MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, 61*29f75a5cSFabio Estevam MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, 62*29f75a5cSFabio Estevam MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, 63*29f75a5cSFabio Estevam MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, 64*29f75a5cSFabio Estevam MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, 65*29f75a5cSFabio Estevam MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, 66*29f75a5cSFabio Estevam MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, 67*29f75a5cSFabio Estevam /* FEC0 Enable */ 68*29f75a5cSFabio Estevam MX28_PAD_SSP1_DATA3__GPIO_2_15 | 69*29f75a5cSFabio Estevam (MXS_PAD_12MA | MXS_PAD_3V3), 70*29f75a5cSFabio Estevam /* FEC0 Reset */ 71*29f75a5cSFabio Estevam MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | 72*29f75a5cSFabio Estevam (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 73*29f75a5cSFabio Estevam 74*29f75a5cSFabio Estevam /* FEC1 */ 75*29f75a5cSFabio Estevam MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET, 76*29f75a5cSFabio Estevam MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET, 77*29f75a5cSFabio Estevam MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET, 78*29f75a5cSFabio Estevam MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET, 79*29f75a5cSFabio Estevam MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET, 80*29f75a5cSFabio Estevam MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET, 81*29f75a5cSFabio Estevam 82*29f75a5cSFabio Estevam /* EMI */ 83*29f75a5cSFabio Estevam MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, 84*29f75a5cSFabio Estevam MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, 85*29f75a5cSFabio Estevam MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, 86*29f75a5cSFabio Estevam MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, 87*29f75a5cSFabio Estevam MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, 88*29f75a5cSFabio Estevam MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, 89*29f75a5cSFabio Estevam MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, 90*29f75a5cSFabio Estevam MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, 91*29f75a5cSFabio Estevam MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, 92*29f75a5cSFabio Estevam MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, 93*29f75a5cSFabio Estevam MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, 94*29f75a5cSFabio Estevam MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, 95*29f75a5cSFabio Estevam MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, 96*29f75a5cSFabio Estevam MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, 97*29f75a5cSFabio Estevam MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, 98*29f75a5cSFabio Estevam MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, 99*29f75a5cSFabio Estevam MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, 100*29f75a5cSFabio Estevam MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, 101*29f75a5cSFabio Estevam MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, 102*29f75a5cSFabio Estevam MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, 103*29f75a5cSFabio Estevam MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, 104*29f75a5cSFabio Estevam MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, 105*29f75a5cSFabio Estevam MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, 106*29f75a5cSFabio Estevam MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, 107*29f75a5cSFabio Estevam MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, 108*29f75a5cSFabio Estevam 109*29f75a5cSFabio Estevam MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, 110*29f75a5cSFabio Estevam MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, 111*29f75a5cSFabio Estevam MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, 112*29f75a5cSFabio Estevam MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, 113*29f75a5cSFabio Estevam MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, 114*29f75a5cSFabio Estevam MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, 115*29f75a5cSFabio Estevam MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, 116*29f75a5cSFabio Estevam MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, 117*29f75a5cSFabio Estevam MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, 118*29f75a5cSFabio Estevam MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, 119*29f75a5cSFabio Estevam MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, 120*29f75a5cSFabio Estevam MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, 121*29f75a5cSFabio Estevam MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, 122*29f75a5cSFabio Estevam MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, 123*29f75a5cSFabio Estevam MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, 124*29f75a5cSFabio Estevam MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, 125*29f75a5cSFabio Estevam MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, 126*29f75a5cSFabio Estevam MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, 127*29f75a5cSFabio Estevam MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, 128*29f75a5cSFabio Estevam MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, 129*29f75a5cSFabio Estevam MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, 130*29f75a5cSFabio Estevam MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, 131*29f75a5cSFabio Estevam MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, 132*29f75a5cSFabio Estevam MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, 133*29f75a5cSFabio Estevam }; 134*29f75a5cSFabio Estevam 135*29f75a5cSFabio Estevam void board_init_ll(void) 136*29f75a5cSFabio Estevam { 137*29f75a5cSFabio Estevam mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); 138*29f75a5cSFabio Estevam } 139