1 /* 2 * Copyright 2006, 2007 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <pci.h> 25 #include <asm/processor.h> 26 #include <asm/immap_86xx.h> 27 #include <asm/fsl_pci.h> 28 #include <asm/fsl_ddr_sdram.h> 29 #include <asm/io.h> 30 #include <libfdt.h> 31 #include <fdt_support.h> 32 #include <netdev.h> 33 34 phys_size_t fixed_sdram(void); 35 36 int board_early_init_f(void) 37 { 38 return 0; 39 } 40 41 int checkboard(void) 42 { 43 u8 vboot; 44 u8 *pixis_base = (u8 *)PIXIS_BASE; 45 46 printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, " 47 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 48 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 49 in_8(pixis_base + PIXIS_PVER)); 50 51 vboot = in_8(pixis_base + PIXIS_VBOOT); 52 if (vboot & PIXIS_VBOOT_FMAP) 53 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6)); 54 else 55 puts ("Promjet\n"); 56 57 #ifdef CONFIG_PHYS_64BIT 58 printf (" 36-bit physical address map\n"); 59 #endif 60 return 0; 61 } 62 63 64 phys_size_t 65 initdram(int board_type) 66 { 67 phys_size_t dram_size = 0; 68 69 #if defined(CONFIG_SPD_EEPROM) 70 dram_size = fsl_ddr_sdram(); 71 #else 72 dram_size = fixed_sdram(); 73 #endif 74 75 setup_ddr_bat(dram_size); 76 77 puts(" DDR: "); 78 return dram_size; 79 } 80 81 82 #if !defined(CONFIG_SPD_EEPROM) 83 /* 84 * Fixed sdram init -- doesn't use serial presence detect. 85 */ 86 phys_size_t 87 fixed_sdram(void) 88 { 89 #if !defined(CONFIG_SYS_RAMBOOT) 90 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 91 volatile ccsr_ddr_t *ddr = &immap->im_ddr1; 92 93 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 94 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 95 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 96 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 97 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 98 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 99 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 100 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 101 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 102 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 103 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 104 ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL; 105 ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS; 106 107 #if defined (CONFIG_DDR_ECC) 108 ddr->err_disable = 0x0000008D; 109 ddr->err_sbe = 0x00ff0000; 110 #endif 111 asm("sync;isync"); 112 113 udelay(500); 114 115 #if defined (CONFIG_DDR_ECC) 116 /* Enable ECC checking */ 117 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); 118 #else 119 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 120 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 121 #endif 122 asm("sync; isync"); 123 124 udelay(500); 125 #endif 126 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 127 } 128 #endif /* !defined(CONFIG_SPD_EEPROM) */ 129 130 131 #if defined(CONFIG_PCI) 132 static struct pci_controller pci1_hose; 133 #endif /* CONFIG_PCI */ 134 135 #ifdef CONFIG_PCI2 136 static struct pci_controller pci2_hose; 137 #endif /* CONFIG_PCI2 */ 138 139 int first_free_busno = 0; 140 141 void pci_init_board(void) 142 { 143 #ifdef CONFIG_PCI1 144 { 145 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; 146 struct pci_controller *hose = &pci1_hose; 147 struct pci_region *r = hose->regions; 148 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; 149 volatile ccsr_gur_t *gur = &immap->im_gur; 150 uint devdisr = gur->devdisr; 151 uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) 152 >> MPC8641_PORDEVSR_IO_SEL_SHIFT; 153 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 154 155 #ifdef DEBUG 156 uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA) 157 >> MPC8641_PORBMSR_HA_SHIFT; 158 uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); 159 #endif 160 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { 161 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); 162 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); 163 if (pci->pme_msg_det) { 164 pci->pme_msg_det = 0xffffffff; 165 debug(" with errors. Clearing. Now 0x%08x", 166 pci->pme_msg_det); 167 } 168 debug("\n"); 169 170 /* outbound memory */ 171 pci_set_region(r++, 172 CONFIG_SYS_PCI1_MEM_BUS, 173 CONFIG_SYS_PCI1_MEM_PHYS, 174 CONFIG_SYS_PCI1_MEM_SIZE, 175 PCI_REGION_MEM); 176 177 /* outbound io */ 178 pci_set_region(r++, 179 CONFIG_SYS_PCI1_IO_BUS, 180 CONFIG_SYS_PCI1_IO_PHYS, 181 CONFIG_SYS_PCI1_IO_SIZE, 182 PCI_REGION_IO); 183 184 hose->region_count = r - hose->regions; 185 186 hose->first_busno=first_free_busno; 187 188 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 189 190 first_free_busno=hose->last_busno+1; 191 printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", 192 hose->first_busno,hose->last_busno); 193 194 /* 195 * Activate ULI1575 legacy chip by performing a fake 196 * memory access. Needed to make ULI RTC work. 197 */ 198 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_VIRT 199 + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000))); 200 201 } else { 202 puts("PCI-EXPRESS 1: Disabled\n"); 203 } 204 } 205 #else 206 puts("PCI-EXPRESS1: Disabled\n"); 207 #endif /* CONFIG_PCI1 */ 208 209 #ifdef CONFIG_PCI2 210 { 211 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR; 212 struct pci_controller *hose = &pci2_hose; 213 struct pci_region *r = hose->regions; 214 215 /* outbound memory */ 216 pci_set_region(r++, 217 CONFIG_SYS_PCI2_MEM_BUS, 218 CONFIG_SYS_PCI2_MEM_PHYS, 219 CONFIG_SYS_PCI2_MEM_SIZE, 220 PCI_REGION_MEM); 221 222 /* outbound io */ 223 pci_set_region(r++, 224 CONFIG_SYS_PCI2_IO_BUS, 225 CONFIG_SYS_PCI2_IO_PHYS, 226 CONFIG_SYS_PCI2_IO_SIZE, 227 PCI_REGION_IO); 228 229 hose->region_count = r - hose->regions; 230 231 hose->first_busno=first_free_busno; 232 233 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 234 235 first_free_busno=hose->last_busno+1; 236 printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", 237 hose->first_busno,hose->last_busno); 238 } 239 #else 240 puts("PCI-EXPRESS 2: Disabled\n"); 241 #endif /* CONFIG_PCI2 */ 242 243 } 244 245 246 #if defined(CONFIG_OF_BOARD_SETUP) 247 void 248 ft_board_setup(void *blob, bd_t *bd) 249 { 250 int off; 251 u64 *tmp; 252 u32 *addrcells; 253 254 ft_cpu_setup(blob, bd); 255 256 #ifdef CONFIG_PCI1 257 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 258 #endif 259 #ifdef CONFIG_PCI2 260 ft_fsl_pci_setup(blob, "pci1", &pci2_hose); 261 #endif 262 263 /* 264 * Warn if it looks like the device tree doesn't match u-boot. 265 * This is just an estimation, based on the location of CCSR, 266 * which is defined by the "reg" property in the soc node. 267 */ 268 off = fdt_path_offset(blob, "/soc8641"); 269 addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL); 270 tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL); 271 272 if (tmp) { 273 u64 addr; 274 if (addrcells && (*addrcells == 1)) 275 addr = *(u32 *)tmp; 276 else 277 addr = *tmp; 278 279 if (addr != CONFIG_SYS_CCSRBAR_PHYS) 280 printf("WARNING: The CCSRBAR address in your .dts " 281 "does not match the address of the CCSR " 282 "in u-boot. This means your .dts might " 283 "be old.\n"); 284 } 285 } 286 #endif 287 288 289 /* 290 * get_board_sys_clk 291 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ 292 */ 293 294 unsigned long 295 get_board_sys_clk(ulong dummy) 296 { 297 u8 i, go_bit, rd_clks; 298 ulong val = 0; 299 u8 *pixis_base = (u8 *)PIXIS_BASE; 300 301 go_bit = in_8(pixis_base + PIXIS_VCTL); 302 go_bit &= 0x01; 303 304 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0); 305 rd_clks &= 0x1C; 306 307 /* 308 * Only if both go bit and the SCLK bit in VCFGEN0 are set 309 * should we be using the AUX register. Remember, we also set the 310 * GO bit to boot from the alternate bank on the on-board flash 311 */ 312 313 if (go_bit) { 314 if (rd_clks == 0x1c) 315 i = in_8(pixis_base + PIXIS_AUX); 316 else 317 i = in_8(pixis_base + PIXIS_SPD); 318 } else { 319 i = in_8(pixis_base + PIXIS_SPD); 320 } 321 322 i &= 0x07; 323 324 switch (i) { 325 case 0: 326 val = 33000000; 327 break; 328 case 1: 329 val = 40000000; 330 break; 331 case 2: 332 val = 50000000; 333 break; 334 case 3: 335 val = 66000000; 336 break; 337 case 4: 338 val = 83000000; 339 break; 340 case 5: 341 val = 100000000; 342 break; 343 case 6: 344 val = 134000000; 345 break; 346 case 7: 347 val = 166000000; 348 break; 349 } 350 351 return val; 352 } 353 354 int board_eth_init(bd_t *bis) 355 { 356 /* Initialize TSECs */ 357 cpu_eth_init(bis); 358 return pci_eth_init(bis); 359 } 360 361 void board_reset(void) 362 { 363 u8 *pixis_base = (u8 *)PIXIS_BASE; 364 365 out_8(pixis_base + PIXIS_RST, 0); 366 367 while (1) 368 ; 369 } 370 371 #ifdef CONFIG_MP 372 extern void cpu_mp_lmb_reserve(struct lmb *lmb); 373 374 void board_lmb_reserve(struct lmb *lmb) 375 { 376 cpu_mp_lmb_reserve(lmb); 377 } 378 #endif 379