1 /* 2 * Copyright 2006, 2007, 2010 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <pci.h> 25 #include <asm/processor.h> 26 #include <asm/immap_86xx.h> 27 #include <asm/fsl_pci.h> 28 #include <asm/fsl_ddr_sdram.h> 29 #include <asm/fsl_serdes.h> 30 #include <asm/io.h> 31 #include <libfdt.h> 32 #include <fdt_support.h> 33 #include <netdev.h> 34 35 phys_size_t fixed_sdram(void); 36 37 int board_early_init_f(void) 38 { 39 return 0; 40 } 41 42 int checkboard(void) 43 { 44 u8 vboot; 45 u8 *pixis_base = (u8 *)PIXIS_BASE; 46 47 printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, " 48 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 49 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 50 in_8(pixis_base + PIXIS_PVER)); 51 52 vboot = in_8(pixis_base + PIXIS_VBOOT); 53 if (vboot & PIXIS_VBOOT_FMAP) 54 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6)); 55 else 56 puts ("Promjet\n"); 57 58 #ifdef CONFIG_PHYS_64BIT 59 printf (" 36-bit physical address map\n"); 60 #endif 61 return 0; 62 } 63 64 phys_size_t 65 initdram(int board_type) 66 { 67 phys_size_t dram_size = 0; 68 69 #if defined(CONFIG_SPD_EEPROM) 70 dram_size = fsl_ddr_sdram(); 71 #else 72 dram_size = fixed_sdram(); 73 #endif 74 75 setup_ddr_bat(dram_size); 76 77 puts(" DDR: "); 78 return dram_size; 79 } 80 81 82 #if !defined(CONFIG_SPD_EEPROM) 83 /* 84 * Fixed sdram init -- doesn't use serial presence detect. 85 */ 86 phys_size_t 87 fixed_sdram(void) 88 { 89 #if !defined(CONFIG_SYS_RAMBOOT) 90 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 91 volatile ccsr_ddr_t *ddr = &immap->im_ddr1; 92 93 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 94 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 95 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 96 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 97 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 98 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 99 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 100 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 101 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 102 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 103 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 104 ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL; 105 ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS; 106 107 #if defined (CONFIG_DDR_ECC) 108 ddr->err_disable = 0x0000008D; 109 ddr->err_sbe = 0x00ff0000; 110 #endif 111 asm("sync;isync"); 112 113 udelay(500); 114 115 #if defined (CONFIG_DDR_ECC) 116 /* Enable ECC checking */ 117 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); 118 #else 119 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 120 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 121 #endif 122 asm("sync; isync"); 123 124 udelay(500); 125 #endif 126 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 127 } 128 #endif /* !defined(CONFIG_SPD_EEPROM) */ 129 130 void pci_init_board(void) 131 { 132 fsl_pcie_init_board(0); 133 134 #ifdef CONFIG_PCIE1 135 /* 136 * Activate ULI1575 legacy chip by performing a fake 137 * memory access. Needed to make ULI RTC work. 138 */ 139 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT 140 + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000))); 141 #endif /* CONFIG_PCIE1 */ 142 } 143 144 145 #if defined(CONFIG_OF_BOARD_SETUP) 146 void 147 ft_board_setup(void *blob, bd_t *bd) 148 { 149 int off; 150 u64 *tmp; 151 u32 *addrcells; 152 153 ft_cpu_setup(blob, bd); 154 155 FT_FSL_PCI_SETUP; 156 157 /* 158 * Warn if it looks like the device tree doesn't match u-boot. 159 * This is just an estimation, based on the location of CCSR, 160 * which is defined by the "reg" property in the soc node. 161 */ 162 off = fdt_path_offset(blob, "/soc8641"); 163 addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL); 164 tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL); 165 166 if (tmp) { 167 u64 addr; 168 if (addrcells && (*addrcells == 1)) 169 addr = *(u32 *)tmp; 170 else 171 addr = *tmp; 172 173 if (addr != CONFIG_SYS_CCSRBAR_PHYS) 174 printf("WARNING: The CCSRBAR address in your .dts " 175 "does not match the address of the CCSR " 176 "in u-boot. This means your .dts might " 177 "be old.\n"); 178 } 179 } 180 #endif 181 182 183 /* 184 * get_board_sys_clk 185 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ 186 */ 187 188 unsigned long 189 get_board_sys_clk(ulong dummy) 190 { 191 u8 i, go_bit, rd_clks; 192 ulong val = 0; 193 u8 *pixis_base = (u8 *)PIXIS_BASE; 194 195 go_bit = in_8(pixis_base + PIXIS_VCTL); 196 go_bit &= 0x01; 197 198 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0); 199 rd_clks &= 0x1C; 200 201 /* 202 * Only if both go bit and the SCLK bit in VCFGEN0 are set 203 * should we be using the AUX register. Remember, we also set the 204 * GO bit to boot from the alternate bank on the on-board flash 205 */ 206 207 if (go_bit) { 208 if (rd_clks == 0x1c) 209 i = in_8(pixis_base + PIXIS_AUX); 210 else 211 i = in_8(pixis_base + PIXIS_SPD); 212 } else { 213 i = in_8(pixis_base + PIXIS_SPD); 214 } 215 216 i &= 0x07; 217 218 switch (i) { 219 case 0: 220 val = 33000000; 221 break; 222 case 1: 223 val = 40000000; 224 break; 225 case 2: 226 val = 50000000; 227 break; 228 case 3: 229 val = 66000000; 230 break; 231 case 4: 232 val = 83000000; 233 break; 234 case 5: 235 val = 100000000; 236 break; 237 case 6: 238 val = 134000000; 239 break; 240 case 7: 241 val = 166000000; 242 break; 243 } 244 245 return val; 246 } 247 248 int board_eth_init(bd_t *bis) 249 { 250 /* Initialize TSECs */ 251 cpu_eth_init(bis); 252 return pci_eth_init(bis); 253 } 254 255 void board_reset(void) 256 { 257 u8 *pixis_base = (u8 *)PIXIS_BASE; 258 259 out_8(pixis_base + PIXIS_RST, 0); 260 261 while (1) 262 ; 263 } 264 265 #ifdef CONFIG_MP 266 extern void cpu_mp_lmb_reserve(struct lmb *lmb); 267 268 void board_lmb_reserve(struct lmb *lmb) 269 { 270 cpu_mp_lmb_reserve(lmb); 271 } 272 #endif 273