1 /* 2 * Copyright 2006, 2007, 2010-2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <pci.h> 9 #include <asm/processor.h> 10 #include <asm/immap_86xx.h> 11 #include <asm/fsl_pci.h> 12 #include <fsl_ddr_sdram.h> 13 #include <asm/fsl_serdes.h> 14 #include <asm/io.h> 15 #include <linux/libfdt.h> 16 #include <fdt_support.h> 17 #include <netdev.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 phys_size_t fixed_sdram(void); 22 23 int checkboard(void) 24 { 25 u8 vboot; 26 u8 *pixis_base = (u8 *)PIXIS_BASE; 27 28 printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, " 29 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 30 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 31 in_8(pixis_base + PIXIS_PVER)); 32 33 vboot = in_8(pixis_base + PIXIS_VBOOT); 34 if (vboot & PIXIS_VBOOT_FMAP) 35 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6)); 36 else 37 puts ("Promjet\n"); 38 39 return 0; 40 } 41 42 int dram_init(void) 43 { 44 phys_size_t dram_size = 0; 45 46 #if defined(CONFIG_SPD_EEPROM) 47 dram_size = fsl_ddr_sdram(); 48 #else 49 dram_size = fixed_sdram(); 50 #endif 51 52 setup_ddr_bat(dram_size); 53 54 debug(" DDR: "); 55 gd->ram_size = dram_size; 56 57 return 0; 58 } 59 60 61 #if !defined(CONFIG_SPD_EEPROM) 62 /* 63 * Fixed sdram init -- doesn't use serial presence detect. 64 */ 65 phys_size_t 66 fixed_sdram(void) 67 { 68 #if !defined(CONFIG_SYS_RAMBOOT) 69 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 70 struct ccsr_ddr __iomem *ddr = &immap->im_ddr1; 71 72 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 73 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 74 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 75 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 76 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 77 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 78 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 79 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 80 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 81 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 82 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 83 ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL; 84 ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS; 85 86 #if defined (CONFIG_DDR_ECC) 87 ddr->err_disable = 0x0000008D; 88 ddr->err_sbe = 0x00ff0000; 89 #endif 90 asm("sync;isync"); 91 92 udelay(500); 93 94 #if defined (CONFIG_DDR_ECC) 95 /* Enable ECC checking */ 96 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); 97 #else 98 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 99 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 100 #endif 101 asm("sync; isync"); 102 103 udelay(500); 104 #endif 105 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 106 } 107 #endif /* !defined(CONFIG_SPD_EEPROM) */ 108 109 void pci_init_board(void) 110 { 111 fsl_pcie_init_board(0); 112 113 #ifdef CONFIG_PCIE1 114 /* 115 * Activate ULI1575 legacy chip by performing a fake 116 * memory access. Needed to make ULI RTC work. 117 */ 118 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT 119 + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000))); 120 #endif /* CONFIG_PCIE1 */ 121 } 122 123 124 #if defined(CONFIG_OF_BOARD_SETUP) 125 int ft_board_setup(void *blob, bd_t *bd) 126 { 127 int off; 128 u64 *tmp; 129 int addrcells; 130 131 ft_cpu_setup(blob, bd); 132 133 FT_FSL_PCI_SETUP; 134 135 /* 136 * Warn if it looks like the device tree doesn't match u-boot. 137 * This is just an estimation, based on the location of CCSR, 138 * which is defined by the "reg" property in the soc node. 139 */ 140 off = fdt_path_offset(blob, "/soc8641"); 141 addrcells = fdt_address_cells(blob, 0); 142 tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL); 143 144 if (tmp) { 145 u64 addr; 146 147 if (addrcells == 1) 148 addr = *(u32 *)tmp; 149 else 150 addr = *tmp; 151 152 if (addr != CONFIG_SYS_CCSRBAR_PHYS) 153 printf("WARNING: The CCSRBAR address in your .dts " 154 "does not match the address of the CCSR " 155 "in u-boot. This means your .dts might " 156 "be old.\n"); 157 } 158 159 return 0; 160 } 161 #endif 162 163 164 /* 165 * get_board_sys_clk 166 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ 167 */ 168 169 unsigned long 170 get_board_sys_clk(ulong dummy) 171 { 172 u8 i, go_bit, rd_clks; 173 ulong val = 0; 174 u8 *pixis_base = (u8 *)PIXIS_BASE; 175 176 go_bit = in_8(pixis_base + PIXIS_VCTL); 177 go_bit &= 0x01; 178 179 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0); 180 rd_clks &= 0x1C; 181 182 /* 183 * Only if both go bit and the SCLK bit in VCFGEN0 are set 184 * should we be using the AUX register. Remember, we also set the 185 * GO bit to boot from the alternate bank on the on-board flash 186 */ 187 188 if (go_bit) { 189 if (rd_clks == 0x1c) 190 i = in_8(pixis_base + PIXIS_AUX); 191 else 192 i = in_8(pixis_base + PIXIS_SPD); 193 } else { 194 i = in_8(pixis_base + PIXIS_SPD); 195 } 196 197 i &= 0x07; 198 199 switch (i) { 200 case 0: 201 val = 33000000; 202 break; 203 case 1: 204 val = 40000000; 205 break; 206 case 2: 207 val = 50000000; 208 break; 209 case 3: 210 val = 66000000; 211 break; 212 case 4: 213 val = 83000000; 214 break; 215 case 5: 216 val = 100000000; 217 break; 218 case 6: 219 val = 134000000; 220 break; 221 case 7: 222 val = 166000000; 223 break; 224 } 225 226 return val; 227 } 228 229 int board_eth_init(bd_t *bis) 230 { 231 /* Initialize TSECs */ 232 cpu_eth_init(bis); 233 return pci_eth_init(bis); 234 } 235 236 void board_reset(void) 237 { 238 u8 *pixis_base = (u8 *)PIXIS_BASE; 239 240 out_8(pixis_base + PIXIS_RST, 0); 241 242 while (1) 243 ; 244 } 245