1 /* 2 * Copyright 2006, 2007 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <pci.h> 25 #include <asm/processor.h> 26 #include <asm/immap_86xx.h> 27 #include <asm/fsl_pci.h> 28 #include <asm/fsl_ddr_sdram.h> 29 #include <asm/io.h> 30 #include <libfdt.h> 31 #include <fdt_support.h> 32 #include <netdev.h> 33 34 #include "../common/pixis.h" 35 36 phys_size_t fixed_sdram(void); 37 38 int board_early_init_f(void) 39 { 40 return 0; 41 } 42 43 int checkboard(void) 44 { 45 u8 vboot; 46 u8 *pixis_base = (u8 *)PIXIS_BASE; 47 48 printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, " 49 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 50 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 51 in_8(pixis_base + PIXIS_PVER)); 52 53 vboot = in_8(pixis_base + PIXIS_VBOOT); 54 if (vboot & PIXIS_VBOOT_FMAP) 55 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6)); 56 else 57 puts ("Promjet\n"); 58 59 #ifdef CONFIG_PHYS_64BIT 60 printf (" 36-bit physical address map\n"); 61 #endif 62 return 0; 63 } 64 65 66 phys_size_t 67 initdram(int board_type) 68 { 69 phys_size_t dram_size = 0; 70 71 #if defined(CONFIG_SPD_EEPROM) 72 dram_size = fsl_ddr_sdram(); 73 #else 74 dram_size = fixed_sdram(); 75 #endif 76 77 #if defined(CONFIG_SYS_RAMBOOT) 78 puts(" DDR: "); 79 return dram_size; 80 #endif 81 82 puts(" DDR: "); 83 return dram_size; 84 } 85 86 87 #if !defined(CONFIG_SPD_EEPROM) 88 /* 89 * Fixed sdram init -- doesn't use serial presence detect. 90 */ 91 phys_size_t 92 fixed_sdram(void) 93 { 94 #if !defined(CONFIG_SYS_RAMBOOT) 95 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 96 volatile ccsr_ddr_t *ddr = &immap->im_ddr1; 97 98 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 99 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 100 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 101 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 102 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 103 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 104 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 105 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 106 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 107 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 108 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 109 ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL; 110 ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS; 111 112 #if defined (CONFIG_DDR_ECC) 113 ddr->err_disable = 0x0000008D; 114 ddr->err_sbe = 0x00ff0000; 115 #endif 116 asm("sync;isync"); 117 118 udelay(500); 119 120 #if defined (CONFIG_DDR_ECC) 121 /* Enable ECC checking */ 122 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); 123 #else 124 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 125 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 126 #endif 127 asm("sync; isync"); 128 129 udelay(500); 130 #endif 131 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 132 } 133 #endif /* !defined(CONFIG_SPD_EEPROM) */ 134 135 136 #if defined(CONFIG_PCI) 137 static struct pci_controller pci1_hose; 138 #endif /* CONFIG_PCI */ 139 140 #ifdef CONFIG_PCI2 141 static struct pci_controller pci2_hose; 142 #endif /* CONFIG_PCI2 */ 143 144 int first_free_busno = 0; 145 146 void pci_init_board(void) 147 { 148 #ifdef CONFIG_PCI1 149 { 150 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; 151 struct pci_controller *hose = &pci1_hose; 152 struct pci_region *r = hose->regions; 153 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; 154 volatile ccsr_gur_t *gur = &immap->im_gur; 155 uint devdisr = gur->devdisr; 156 uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) 157 >> MPC8641_PORDEVSR_IO_SEL_SHIFT; 158 159 #ifdef DEBUG 160 uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA) 161 >> MPC8641_PORBMSR_HA_SHIFT; 162 uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); 163 #endif 164 if ((io_sel == 2 || io_sel == 3 || io_sel == 5 165 || io_sel == 6 || io_sel == 7 || io_sel == 0xF) 166 && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { 167 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); 168 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); 169 if (pci->pme_msg_det) { 170 pci->pme_msg_det = 0xffffffff; 171 debug(" with errors. Clearing. Now 0x%08x", 172 pci->pme_msg_det); 173 } 174 debug("\n"); 175 176 /* outbound memory */ 177 pci_set_region(r++, 178 CONFIG_SYS_PCI1_MEM_BUS, 179 CONFIG_SYS_PCI1_MEM_PHYS, 180 CONFIG_SYS_PCI1_MEM_SIZE, 181 PCI_REGION_MEM); 182 183 /* outbound io */ 184 pci_set_region(r++, 185 CONFIG_SYS_PCI1_IO_BUS, 186 CONFIG_SYS_PCI1_IO_PHYS, 187 CONFIG_SYS_PCI1_IO_SIZE, 188 PCI_REGION_IO); 189 190 /* inbound */ 191 r += fsl_pci_setup_inbound_windows(r); 192 193 hose->region_count = r - hose->regions; 194 195 hose->first_busno=first_free_busno; 196 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 197 198 fsl_pci_init(hose); 199 200 first_free_busno=hose->last_busno+1; 201 printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", 202 hose->first_busno,hose->last_busno); 203 204 /* 205 * Activate ULI1575 legacy chip by performing a fake 206 * memory access. Needed to make ULI RTC work. 207 */ 208 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_VIRT 209 + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000))); 210 211 } else { 212 puts("PCI-EXPRESS 1: Disabled\n"); 213 } 214 } 215 #else 216 puts("PCI-EXPRESS1: Disabled\n"); 217 #endif /* CONFIG_PCI1 */ 218 219 #ifdef CONFIG_PCI2 220 { 221 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR; 222 struct pci_controller *hose = &pci2_hose; 223 struct pci_region *r = hose->regions; 224 225 /* outbound memory */ 226 pci_set_region(r++, 227 CONFIG_SYS_PCI2_MEM_BUS, 228 CONFIG_SYS_PCI2_MEM_PHYS, 229 CONFIG_SYS_PCI2_MEM_SIZE, 230 PCI_REGION_MEM); 231 232 /* outbound io */ 233 pci_set_region(r++, 234 CONFIG_SYS_PCI2_IO_BUS, 235 CONFIG_SYS_PCI2_IO_PHYS, 236 CONFIG_SYS_PCI2_IO_SIZE, 237 PCI_REGION_IO); 238 239 /* inbound */ 240 r += fsl_pci_setup_inbound_windows(r); 241 242 hose->region_count = r - hose->regions; 243 244 hose->first_busno=first_free_busno; 245 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 246 247 fsl_pci_init(hose); 248 249 first_free_busno=hose->last_busno+1; 250 printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", 251 hose->first_busno,hose->last_busno); 252 } 253 #else 254 puts("PCI-EXPRESS 2: Disabled\n"); 255 #endif /* CONFIG_PCI2 */ 256 257 } 258 259 260 #if defined(CONFIG_OF_BOARD_SETUP) 261 void 262 ft_board_setup(void *blob, bd_t *bd) 263 { 264 int off; 265 u64 *tmp; 266 u32 *addrcells; 267 268 ft_cpu_setup(blob, bd); 269 270 #ifdef CONFIG_PCI1 271 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 272 #endif 273 #ifdef CONFIG_PCI2 274 ft_fsl_pci_setup(blob, "pci1", &pci2_hose); 275 #endif 276 277 /* 278 * Warn if it looks like the device tree doesn't match u-boot. 279 * This is just an estimation, based on the location of CCSR, 280 * which is defined by the "reg" property in the soc node. 281 */ 282 off = fdt_path_offset(blob, "/soc8641"); 283 addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL); 284 tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL); 285 286 if (tmp) { 287 u64 addr; 288 if (addrcells && (*addrcells == 1)) 289 addr = *(u32 *)tmp; 290 else 291 addr = *tmp; 292 293 if (addr != CONFIG_SYS_CCSRBAR_PHYS) 294 printf("WARNING: The CCSRBAR address in your .dts " 295 "does not match the address of the CCSR " 296 "in u-boot. This means your .dts might " 297 "be old.\n"); 298 } 299 } 300 #endif 301 302 303 /* 304 * get_board_sys_clk 305 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ 306 */ 307 308 unsigned long 309 get_board_sys_clk(ulong dummy) 310 { 311 u8 i, go_bit, rd_clks; 312 ulong val = 0; 313 u8 *pixis_base = (u8 *)PIXIS_BASE; 314 315 go_bit = in_8(pixis_base + PIXIS_VCTL); 316 go_bit &= 0x01; 317 318 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0); 319 rd_clks &= 0x1C; 320 321 /* 322 * Only if both go bit and the SCLK bit in VCFGEN0 are set 323 * should we be using the AUX register. Remember, we also set the 324 * GO bit to boot from the alternate bank on the on-board flash 325 */ 326 327 if (go_bit) { 328 if (rd_clks == 0x1c) 329 i = in_8(pixis_base + PIXIS_AUX); 330 else 331 i = in_8(pixis_base + PIXIS_SPD); 332 } else { 333 i = in_8(pixis_base + PIXIS_SPD); 334 } 335 336 i &= 0x07; 337 338 switch (i) { 339 case 0: 340 val = 33000000; 341 break; 342 case 1: 343 val = 40000000; 344 break; 345 case 2: 346 val = 50000000; 347 break; 348 case 3: 349 val = 66000000; 350 break; 351 case 4: 352 val = 83000000; 353 break; 354 case 5: 355 val = 100000000; 356 break; 357 case 6: 358 val = 134000000; 359 break; 360 case 7: 361 val = 166000000; 362 break; 363 } 364 365 return val; 366 } 367 368 int board_eth_init(bd_t *bis) 369 { 370 /* Initialize TSECs */ 371 cpu_eth_init(bis); 372 return pci_eth_init(bis); 373 } 374 375 void board_reset(void) 376 { 377 u8 *pixis_base = (u8 *)PIXIS_BASE; 378 379 out_8(pixis_base + PIXIS_RST, 0); 380 381 while (1) 382 ; 383 } 384 385 #ifdef CONFIG_MP 386 extern void cpu_mp_lmb_reserve(struct lmb *lmb); 387 388 void board_lmb_reserve(struct lmb *lmb) 389 { 390 cpu_mp_lmb_reserve(lmb); 391 } 392 #endif 393