1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2006, 2007, 2010-2011 Freescale Semiconductor. 4 */ 5 6 #include <common.h> 7 #include <pci.h> 8 #include <asm/processor.h> 9 #include <asm/immap_86xx.h> 10 #include <asm/fsl_pci.h> 11 #include <fsl_ddr_sdram.h> 12 #include <asm/fsl_serdes.h> 13 #include <asm/io.h> 14 #include <linux/libfdt.h> 15 #include <fdt_support.h> 16 #include <netdev.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 phys_size_t fixed_sdram(void); 21 22 int checkboard(void) 23 { 24 u8 vboot; 25 u8 *pixis_base = (u8 *)PIXIS_BASE; 26 27 printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, " 28 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 29 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 30 in_8(pixis_base + PIXIS_PVER)); 31 32 vboot = in_8(pixis_base + PIXIS_VBOOT); 33 if (vboot & PIXIS_VBOOT_FMAP) 34 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6)); 35 else 36 puts ("Promjet\n"); 37 38 return 0; 39 } 40 41 int dram_init(void) 42 { 43 phys_size_t dram_size = 0; 44 45 #if defined(CONFIG_SPD_EEPROM) 46 dram_size = fsl_ddr_sdram(); 47 #else 48 dram_size = fixed_sdram(); 49 #endif 50 51 setup_ddr_bat(dram_size); 52 53 debug(" DDR: "); 54 gd->ram_size = dram_size; 55 56 return 0; 57 } 58 59 60 #if !defined(CONFIG_SPD_EEPROM) 61 /* 62 * Fixed sdram init -- doesn't use serial presence detect. 63 */ 64 phys_size_t 65 fixed_sdram(void) 66 { 67 #if !defined(CONFIG_SYS_RAMBOOT) 68 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 69 struct ccsr_ddr __iomem *ddr = &immap->im_ddr1; 70 71 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 72 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 73 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 74 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 75 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 76 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 77 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 78 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 79 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 80 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 81 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 82 ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL; 83 ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS; 84 85 #if defined (CONFIG_DDR_ECC) 86 ddr->err_disable = 0x0000008D; 87 ddr->err_sbe = 0x00ff0000; 88 #endif 89 asm("sync;isync"); 90 91 udelay(500); 92 93 #if defined (CONFIG_DDR_ECC) 94 /* Enable ECC checking */ 95 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); 96 #else 97 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 98 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 99 #endif 100 asm("sync; isync"); 101 102 udelay(500); 103 #endif 104 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 105 } 106 #endif /* !defined(CONFIG_SPD_EEPROM) */ 107 108 void pci_init_board(void) 109 { 110 fsl_pcie_init_board(0); 111 112 #ifdef CONFIG_PCIE1 113 /* 114 * Activate ULI1575 legacy chip by performing a fake 115 * memory access. Needed to make ULI RTC work. 116 */ 117 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT 118 + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000))); 119 #endif /* CONFIG_PCIE1 */ 120 } 121 122 123 #if defined(CONFIG_OF_BOARD_SETUP) 124 int ft_board_setup(void *blob, bd_t *bd) 125 { 126 int off; 127 u64 *tmp; 128 int addrcells; 129 130 ft_cpu_setup(blob, bd); 131 132 FT_FSL_PCI_SETUP; 133 134 /* 135 * Warn if it looks like the device tree doesn't match u-boot. 136 * This is just an estimation, based on the location of CCSR, 137 * which is defined by the "reg" property in the soc node. 138 */ 139 off = fdt_path_offset(blob, "/soc8641"); 140 addrcells = fdt_address_cells(blob, 0); 141 tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL); 142 143 if (tmp) { 144 u64 addr; 145 146 if (addrcells == 1) 147 addr = *(u32 *)tmp; 148 else 149 addr = *tmp; 150 151 if (addr != CONFIG_SYS_CCSRBAR_PHYS) 152 printf("WARNING: The CCSRBAR address in your .dts " 153 "does not match the address of the CCSR " 154 "in u-boot. This means your .dts might " 155 "be old.\n"); 156 } 157 158 return 0; 159 } 160 #endif 161 162 163 /* 164 * get_board_sys_clk 165 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ 166 */ 167 168 unsigned long 169 get_board_sys_clk(ulong dummy) 170 { 171 u8 i, go_bit, rd_clks; 172 ulong val = 0; 173 u8 *pixis_base = (u8 *)PIXIS_BASE; 174 175 go_bit = in_8(pixis_base + PIXIS_VCTL); 176 go_bit &= 0x01; 177 178 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0); 179 rd_clks &= 0x1C; 180 181 /* 182 * Only if both go bit and the SCLK bit in VCFGEN0 are set 183 * should we be using the AUX register. Remember, we also set the 184 * GO bit to boot from the alternate bank on the on-board flash 185 */ 186 187 if (go_bit) { 188 if (rd_clks == 0x1c) 189 i = in_8(pixis_base + PIXIS_AUX); 190 else 191 i = in_8(pixis_base + PIXIS_SPD); 192 } else { 193 i = in_8(pixis_base + PIXIS_SPD); 194 } 195 196 i &= 0x07; 197 198 switch (i) { 199 case 0: 200 val = 33000000; 201 break; 202 case 1: 203 val = 40000000; 204 break; 205 case 2: 206 val = 50000000; 207 break; 208 case 3: 209 val = 66000000; 210 break; 211 case 4: 212 val = 83000000; 213 break; 214 case 5: 215 val = 100000000; 216 break; 217 case 6: 218 val = 134000000; 219 break; 220 case 7: 221 val = 166000000; 222 break; 223 } 224 225 return val; 226 } 227 228 int board_eth_init(bd_t *bis) 229 { 230 /* Initialize TSECs */ 231 cpu_eth_init(bis); 232 return pci_eth_init(bis); 233 } 234 235 void board_reset(void) 236 { 237 u8 *pixis_base = (u8 *)PIXIS_BASE; 238 239 out_8(pixis_base + PIXIS_RST, 0); 240 241 while (1) 242 ; 243 } 244