1 /* 2 * Copyright 2006, 2007, 2010 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <pci.h> 25 #include <asm/processor.h> 26 #include <asm/immap_86xx.h> 27 #include <asm/fsl_pci.h> 28 #include <asm/fsl_ddr_sdram.h> 29 #include <asm/io.h> 30 #include <libfdt.h> 31 #include <fdt_support.h> 32 #include <netdev.h> 33 34 phys_size_t fixed_sdram(void); 35 36 int board_early_init_f(void) 37 { 38 return 0; 39 } 40 41 int checkboard(void) 42 { 43 u8 vboot; 44 u8 *pixis_base = (u8 *)PIXIS_BASE; 45 46 printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, " 47 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 48 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 49 in_8(pixis_base + PIXIS_PVER)); 50 51 vboot = in_8(pixis_base + PIXIS_VBOOT); 52 if (vboot & PIXIS_VBOOT_FMAP) 53 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6)); 54 else 55 puts ("Promjet\n"); 56 57 #ifdef CONFIG_PHYS_64BIT 58 printf (" 36-bit physical address map\n"); 59 #endif 60 return 0; 61 } 62 63 const char *board_hwconfig = "foo:bar=baz"; 64 const char *cpu_hwconfig = "foo:bar=baz"; 65 66 phys_size_t 67 initdram(int board_type) 68 { 69 phys_size_t dram_size = 0; 70 71 #if defined(CONFIG_SPD_EEPROM) 72 dram_size = fsl_ddr_sdram(); 73 #else 74 dram_size = fixed_sdram(); 75 #endif 76 77 setup_ddr_bat(dram_size); 78 79 puts(" DDR: "); 80 return dram_size; 81 } 82 83 84 #if !defined(CONFIG_SPD_EEPROM) 85 /* 86 * Fixed sdram init -- doesn't use serial presence detect. 87 */ 88 phys_size_t 89 fixed_sdram(void) 90 { 91 #if !defined(CONFIG_SYS_RAMBOOT) 92 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 93 volatile ccsr_ddr_t *ddr = &immap->im_ddr1; 94 95 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 96 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 97 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 98 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 99 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 100 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 101 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 102 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 103 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 104 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 105 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 106 ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL; 107 ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS; 108 109 #if defined (CONFIG_DDR_ECC) 110 ddr->err_disable = 0x0000008D; 111 ddr->err_sbe = 0x00ff0000; 112 #endif 113 asm("sync;isync"); 114 115 udelay(500); 116 117 #if defined (CONFIG_DDR_ECC) 118 /* Enable ECC checking */ 119 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); 120 #else 121 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 122 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 123 #endif 124 asm("sync; isync"); 125 126 udelay(500); 127 #endif 128 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 129 } 130 #endif /* !defined(CONFIG_SPD_EEPROM) */ 131 132 133 #if defined(CONFIG_PCI) 134 static struct pci_controller pcie1_hose; 135 #endif /* CONFIG_PCI */ 136 137 #ifdef CONFIG_PCIE2 138 static struct pci_controller pcie2_hose; 139 #endif /* CONFIG_PCIE2 */ 140 141 int first_free_busno = 0; 142 143 void pci_init_board(void) 144 { 145 struct fsl_pci_info pci_info[2]; 146 int pcie_ep; 147 int num = 0; 148 149 #ifdef CONFIG_PCIE1 150 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; 151 volatile ccsr_gur_t *gur = &immap->im_gur; 152 uint devdisr = in_be32(&gur->devdisr); 153 uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) 154 >> MPC8641_PORDEVSR_IO_SEL_SHIFT; 155 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 156 157 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { 158 SET_STD_PCIE_INFO(pci_info[num], 1); 159 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 160 printf("PCIE1: connected to ULI as %s (base addr %lx)\n", 161 pcie_ep ? "Endpoint" : "Root Complex", 162 pci_info[num].regs); 163 first_free_busno = fsl_pci_init_port(&pci_info[num++], 164 &pcie1_hose, first_free_busno); 165 166 /* 167 * Activate ULI1575 legacy chip by performing a fake 168 * memory access. Needed to make ULI RTC work. 169 */ 170 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT 171 + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000))); 172 173 } else { 174 puts("PCIE1: disabled\n"); 175 } 176 #else 177 puts("PCIE1: disabled\n"); 178 #endif /* CONFIG_PCIE1 */ 179 180 #ifdef CONFIG_PCIE2 181 SET_STD_PCIE_INFO(pci_info[num], 2); 182 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); 183 printf("PCIE2: connected as %s (base addr %lx)\n", 184 pcie_ep ? "Endpoint" : "Root Complex", 185 pci_info[num].regs); 186 first_free_busno = fsl_pci_init_port(&pci_info[num++], 187 &pcie2_hose, first_free_busno); 188 #else 189 puts("PCIE2: disabled\n"); 190 #endif /* CONFIG_PCIE2 */ 191 192 } 193 194 195 #if defined(CONFIG_OF_BOARD_SETUP) 196 void 197 ft_board_setup(void *blob, bd_t *bd) 198 { 199 int off; 200 u64 *tmp; 201 u32 *addrcells; 202 203 ft_cpu_setup(blob, bd); 204 205 FT_FSL_PCI_SETUP; 206 207 /* 208 * Warn if it looks like the device tree doesn't match u-boot. 209 * This is just an estimation, based on the location of CCSR, 210 * which is defined by the "reg" property in the soc node. 211 */ 212 off = fdt_path_offset(blob, "/soc8641"); 213 addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL); 214 tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL); 215 216 if (tmp) { 217 u64 addr; 218 if (addrcells && (*addrcells == 1)) 219 addr = *(u32 *)tmp; 220 else 221 addr = *tmp; 222 223 if (addr != CONFIG_SYS_CCSRBAR_PHYS) 224 printf("WARNING: The CCSRBAR address in your .dts " 225 "does not match the address of the CCSR " 226 "in u-boot. This means your .dts might " 227 "be old.\n"); 228 } 229 } 230 #endif 231 232 233 /* 234 * get_board_sys_clk 235 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ 236 */ 237 238 unsigned long 239 get_board_sys_clk(ulong dummy) 240 { 241 u8 i, go_bit, rd_clks; 242 ulong val = 0; 243 u8 *pixis_base = (u8 *)PIXIS_BASE; 244 245 go_bit = in_8(pixis_base + PIXIS_VCTL); 246 go_bit &= 0x01; 247 248 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0); 249 rd_clks &= 0x1C; 250 251 /* 252 * Only if both go bit and the SCLK bit in VCFGEN0 are set 253 * should we be using the AUX register. Remember, we also set the 254 * GO bit to boot from the alternate bank on the on-board flash 255 */ 256 257 if (go_bit) { 258 if (rd_clks == 0x1c) 259 i = in_8(pixis_base + PIXIS_AUX); 260 else 261 i = in_8(pixis_base + PIXIS_SPD); 262 } else { 263 i = in_8(pixis_base + PIXIS_SPD); 264 } 265 266 i &= 0x07; 267 268 switch (i) { 269 case 0: 270 val = 33000000; 271 break; 272 case 1: 273 val = 40000000; 274 break; 275 case 2: 276 val = 50000000; 277 break; 278 case 3: 279 val = 66000000; 280 break; 281 case 4: 282 val = 83000000; 283 break; 284 case 5: 285 val = 100000000; 286 break; 287 case 6: 288 val = 134000000; 289 break; 290 case 7: 291 val = 166000000; 292 break; 293 } 294 295 return val; 296 } 297 298 int board_eth_init(bd_t *bis) 299 { 300 /* Initialize TSECs */ 301 cpu_eth_init(bis); 302 return pci_eth_init(bis); 303 } 304 305 void board_reset(void) 306 { 307 u8 *pixis_base = (u8 *)PIXIS_BASE; 308 309 out_8(pixis_base + PIXIS_RST, 0); 310 311 while (1) 312 ; 313 } 314 315 #ifdef CONFIG_MP 316 extern void cpu_mp_lmb_reserve(struct lmb *lmb); 317 318 void board_lmb_reserve(struct lmb *lmb) 319 { 320 cpu_mp_lmb_reserve(lmb); 321 } 322 #endif 323