1 /* 2 * Copyright 2006, 2007, 2010 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <pci.h> 25 #include <asm/processor.h> 26 #include <asm/immap_86xx.h> 27 #include <asm/fsl_pci.h> 28 #include <asm/fsl_ddr_sdram.h> 29 #include <asm/fsl_serdes.h> 30 #include <asm/io.h> 31 #include <libfdt.h> 32 #include <fdt_support.h> 33 #include <netdev.h> 34 35 phys_size_t fixed_sdram(void); 36 37 int board_early_init_f(void) 38 { 39 return 0; 40 } 41 42 int checkboard(void) 43 { 44 u8 vboot; 45 u8 *pixis_base = (u8 *)PIXIS_BASE; 46 47 printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, " 48 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 49 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 50 in_8(pixis_base + PIXIS_PVER)); 51 52 vboot = in_8(pixis_base + PIXIS_VBOOT); 53 if (vboot & PIXIS_VBOOT_FMAP) 54 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6)); 55 else 56 puts ("Promjet\n"); 57 58 #ifdef CONFIG_PHYS_64BIT 59 printf (" 36-bit physical address map\n"); 60 #endif 61 return 0; 62 } 63 64 phys_size_t 65 initdram(int board_type) 66 { 67 phys_size_t dram_size = 0; 68 69 #if defined(CONFIG_SPD_EEPROM) 70 dram_size = fsl_ddr_sdram(); 71 #else 72 dram_size = fixed_sdram(); 73 #endif 74 75 setup_ddr_bat(dram_size); 76 77 puts(" DDR: "); 78 return dram_size; 79 } 80 81 82 #if !defined(CONFIG_SPD_EEPROM) 83 /* 84 * Fixed sdram init -- doesn't use serial presence detect. 85 */ 86 phys_size_t 87 fixed_sdram(void) 88 { 89 #if !defined(CONFIG_SYS_RAMBOOT) 90 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 91 volatile ccsr_ddr_t *ddr = &immap->im_ddr1; 92 93 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 94 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 95 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 96 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 97 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 98 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 99 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 100 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 101 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 102 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 103 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 104 ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL; 105 ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS; 106 107 #if defined (CONFIG_DDR_ECC) 108 ddr->err_disable = 0x0000008D; 109 ddr->err_sbe = 0x00ff0000; 110 #endif 111 asm("sync;isync"); 112 113 udelay(500); 114 115 #if defined (CONFIG_DDR_ECC) 116 /* Enable ECC checking */ 117 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); 118 #else 119 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 120 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 121 #endif 122 asm("sync; isync"); 123 124 udelay(500); 125 #endif 126 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 127 } 128 #endif /* !defined(CONFIG_SPD_EEPROM) */ 129 130 131 #if defined(CONFIG_PCI) 132 static struct pci_controller pcie1_hose; 133 #endif /* CONFIG_PCI */ 134 135 #ifdef CONFIG_PCIE2 136 static struct pci_controller pcie2_hose; 137 #endif /* CONFIG_PCIE2 */ 138 139 int first_free_busno = 0; 140 141 void pci_init_board(void) 142 { 143 struct fsl_pci_info pci_info[2]; 144 int pcie_ep; 145 int num = 0; 146 147 #ifdef CONFIG_PCIE1 148 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; 149 volatile ccsr_gur_t *gur = &immap->im_gur; 150 uint devdisr = in_be32(&gur->devdisr); 151 int pcie_configured = is_serdes_configured(PCIE1); 152 153 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { 154 SET_STD_PCIE_INFO(pci_info[num], 1); 155 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 156 printf("PCIE1: connected to ULI as %s (base addr %lx)\n", 157 pcie_ep ? "Endpoint" : "Root Complex", 158 pci_info[num].regs); 159 first_free_busno = fsl_pci_init_port(&pci_info[num++], 160 &pcie1_hose, first_free_busno); 161 162 /* 163 * Activate ULI1575 legacy chip by performing a fake 164 * memory access. Needed to make ULI RTC work. 165 */ 166 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT 167 + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000))); 168 169 } else { 170 puts("PCIE1: disabled\n"); 171 } 172 #else 173 puts("PCIE1: disabled\n"); 174 #endif /* CONFIG_PCIE1 */ 175 176 #ifdef CONFIG_PCIE2 177 SET_STD_PCIE_INFO(pci_info[num], 2); 178 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); 179 printf("PCIE2: connected as %s (base addr %lx)\n", 180 pcie_ep ? "Endpoint" : "Root Complex", 181 pci_info[num].regs); 182 first_free_busno = fsl_pci_init_port(&pci_info[num++], 183 &pcie2_hose, first_free_busno); 184 #else 185 puts("PCIE2: disabled\n"); 186 #endif /* CONFIG_PCIE2 */ 187 188 } 189 190 191 #if defined(CONFIG_OF_BOARD_SETUP) 192 void 193 ft_board_setup(void *blob, bd_t *bd) 194 { 195 int off; 196 u64 *tmp; 197 u32 *addrcells; 198 199 ft_cpu_setup(blob, bd); 200 201 FT_FSL_PCI_SETUP; 202 203 /* 204 * Warn if it looks like the device tree doesn't match u-boot. 205 * This is just an estimation, based on the location of CCSR, 206 * which is defined by the "reg" property in the soc node. 207 */ 208 off = fdt_path_offset(blob, "/soc8641"); 209 addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL); 210 tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL); 211 212 if (tmp) { 213 u64 addr; 214 if (addrcells && (*addrcells == 1)) 215 addr = *(u32 *)tmp; 216 else 217 addr = *tmp; 218 219 if (addr != CONFIG_SYS_CCSRBAR_PHYS) 220 printf("WARNING: The CCSRBAR address in your .dts " 221 "does not match the address of the CCSR " 222 "in u-boot. This means your .dts might " 223 "be old.\n"); 224 } 225 } 226 #endif 227 228 229 /* 230 * get_board_sys_clk 231 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ 232 */ 233 234 unsigned long 235 get_board_sys_clk(ulong dummy) 236 { 237 u8 i, go_bit, rd_clks; 238 ulong val = 0; 239 u8 *pixis_base = (u8 *)PIXIS_BASE; 240 241 go_bit = in_8(pixis_base + PIXIS_VCTL); 242 go_bit &= 0x01; 243 244 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0); 245 rd_clks &= 0x1C; 246 247 /* 248 * Only if both go bit and the SCLK bit in VCFGEN0 are set 249 * should we be using the AUX register. Remember, we also set the 250 * GO bit to boot from the alternate bank on the on-board flash 251 */ 252 253 if (go_bit) { 254 if (rd_clks == 0x1c) 255 i = in_8(pixis_base + PIXIS_AUX); 256 else 257 i = in_8(pixis_base + PIXIS_SPD); 258 } else { 259 i = in_8(pixis_base + PIXIS_SPD); 260 } 261 262 i &= 0x07; 263 264 switch (i) { 265 case 0: 266 val = 33000000; 267 break; 268 case 1: 269 val = 40000000; 270 break; 271 case 2: 272 val = 50000000; 273 break; 274 case 3: 275 val = 66000000; 276 break; 277 case 4: 278 val = 83000000; 279 break; 280 case 5: 281 val = 100000000; 282 break; 283 case 6: 284 val = 134000000; 285 break; 286 case 7: 287 val = 166000000; 288 break; 289 } 290 291 return val; 292 } 293 294 int board_eth_init(bd_t *bis) 295 { 296 /* Initialize TSECs */ 297 cpu_eth_init(bis); 298 return pci_eth_init(bis); 299 } 300 301 void board_reset(void) 302 { 303 u8 *pixis_base = (u8 *)PIXIS_BASE; 304 305 out_8(pixis_base + PIXIS_RST, 0); 306 307 while (1) 308 ; 309 } 310 311 #ifdef CONFIG_MP 312 extern void cpu_mp_lmb_reserve(struct lmb *lmb); 313 314 void board_lmb_reserve(struct lmb *lmb) 315 { 316 cpu_mp_lmb_reserve(lmb); 317 } 318 #endif 319