1 /* 2 * Copyright 2006, 2007 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <pci.h> 25 #include <asm/processor.h> 26 #include <asm/immap_86xx.h> 27 #include <asm/immap_fsl_pci.h> 28 #include <spd.h> 29 #include <asm/io.h> 30 #include <libfdt.h> 31 #include <fdt_support.h> 32 33 #include "../common/pixis.h" 34 35 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 36 extern void ddr_enable_ecc(unsigned int dram_size); 37 #endif 38 39 #if defined(CONFIG_SPD_EEPROM) 40 #include "spd_sdram.h" 41 #endif 42 43 void sdram_init(void); 44 long int fixed_sdram(void); 45 46 47 int board_early_init_f(void) 48 { 49 return 0; 50 } 51 52 int checkboard(void) 53 { 54 puts("Board: MPC8641HPCN\n"); 55 56 return 0; 57 } 58 59 60 long int 61 initdram(int board_type) 62 { 63 long dram_size = 0; 64 65 #if defined(CONFIG_SPD_EEPROM) 66 dram_size = spd_sdram(); 67 #else 68 dram_size = fixed_sdram(); 69 #endif 70 71 #if defined(CFG_RAMBOOT) 72 puts(" DDR: "); 73 return dram_size; 74 #endif 75 76 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 77 /* 78 * Initialize and enable DDR ECC. 79 */ 80 ddr_enable_ecc(dram_size); 81 #endif 82 83 puts(" DDR: "); 84 return dram_size; 85 } 86 87 88 #if defined(CFG_DRAM_TEST) 89 int 90 testdram(void) 91 { 92 uint *pstart = (uint *) CFG_MEMTEST_START; 93 uint *pend = (uint *) CFG_MEMTEST_END; 94 uint *p; 95 96 puts("SDRAM test phase 1:\n"); 97 for (p = pstart; p < pend; p++) 98 *p = 0xaaaaaaaa; 99 100 for (p = pstart; p < pend; p++) { 101 if (*p != 0xaaaaaaaa) { 102 printf("SDRAM test fails at: %08x\n", (uint) p); 103 return 1; 104 } 105 } 106 107 puts("SDRAM test phase 2:\n"); 108 for (p = pstart; p < pend; p++) 109 *p = 0x55555555; 110 111 for (p = pstart; p < pend; p++) { 112 if (*p != 0x55555555) { 113 printf("SDRAM test fails at: %08x\n", (uint) p); 114 return 1; 115 } 116 } 117 118 puts("SDRAM test passed.\n"); 119 return 0; 120 } 121 #endif 122 123 124 #if !defined(CONFIG_SPD_EEPROM) 125 /* 126 * Fixed sdram init -- doesn't use serial presence detect. 127 */ 128 long int 129 fixed_sdram(void) 130 { 131 #if !defined(CFG_RAMBOOT) 132 volatile immap_t *immap = (immap_t *) CFG_IMMR; 133 volatile ccsr_ddr_t *ddr = &immap->im_ddr1; 134 135 ddr->cs0_bnds = CFG_DDR_CS0_BNDS; 136 ddr->cs0_config = CFG_DDR_CS0_CONFIG; 137 ddr->ext_refrec = CFG_DDR_EXT_REFRESH; 138 ddr->timing_cfg_0 = CFG_DDR_TIMING_0; 139 ddr->timing_cfg_1 = CFG_DDR_TIMING_1; 140 ddr->timing_cfg_2 = CFG_DDR_TIMING_2; 141 ddr->sdram_mode_1 = CFG_DDR_MODE_1; 142 ddr->sdram_mode_2 = CFG_DDR_MODE_2; 143 ddr->sdram_interval = CFG_DDR_INTERVAL; 144 ddr->sdram_data_init = CFG_DDR_DATA_INIT; 145 ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; 146 ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL; 147 ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS; 148 149 #if defined (CONFIG_DDR_ECC) 150 ddr->err_disable = 0x0000008D; 151 ddr->err_sbe = 0x00ff0000; 152 #endif 153 asm("sync;isync"); 154 155 udelay(500); 156 157 #if defined (CONFIG_DDR_ECC) 158 /* Enable ECC checking */ 159 ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000); 160 #else 161 ddr->sdram_cfg_1 = CFG_DDR_CONTROL; 162 ddr->sdram_cfg_2 = CFG_DDR_CONTROL2; 163 #endif 164 asm("sync; isync"); 165 166 udelay(500); 167 #endif 168 return CFG_SDRAM_SIZE * 1024 * 1024; 169 } 170 #endif /* !defined(CONFIG_SPD_EEPROM) */ 171 172 173 #if defined(CONFIG_PCI) 174 /* 175 * Initialize PCI Devices, report devices found. 176 */ 177 178 #ifndef CONFIG_PCI_PNP 179 static struct pci_config_table pci_fsl86xxads_config_table[] = { 180 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 181 PCI_IDSEL_NUMBER, PCI_ANY_ID, 182 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 183 PCI_ENET0_MEMADDR, 184 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, 185 {} 186 }; 187 #endif 188 189 190 static struct pci_controller pci1_hose = { 191 #ifndef CONFIG_PCI_PNP 192 config_table:pci_mpc86xxcts_config_table 193 #endif 194 }; 195 #endif /* CONFIG_PCI */ 196 197 #ifdef CONFIG_PCI2 198 static struct pci_controller pci2_hose; 199 #endif /* CONFIG_PCI2 */ 200 201 int first_free_busno = 0; 202 203 204 void pci_init_board(void) 205 { 206 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; 207 volatile ccsr_gur_t *gur = &immap->im_gur; 208 uint devdisr = gur->devdisr; 209 uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; 210 211 #ifdef CONFIG_PCI1 212 { 213 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; 214 extern void fsl_pci_init(struct pci_controller *hose); 215 struct pci_controller *hose = &pci1_hose; 216 #ifdef DEBUG 217 uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; 218 uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); 219 #endif 220 if ((io_sel == 2 || io_sel == 3 || io_sel == 5 221 || io_sel == 6 || io_sel == 7 || io_sel == 0xF) 222 && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { 223 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); 224 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); 225 if (pci->pme_msg_det) { 226 pci->pme_msg_det = 0xffffffff; 227 debug(" with errors. Clearing. Now 0x%08x", 228 pci->pme_msg_det); 229 } 230 debug("\n"); 231 232 /* inbound */ 233 pci_set_region(hose->regions + 0, 234 CFG_PCI_MEMORY_BUS, 235 CFG_PCI_MEMORY_PHYS, 236 CFG_PCI_MEMORY_SIZE, 237 PCI_REGION_MEM | PCI_REGION_MEMORY); 238 239 /* outbound memory */ 240 pci_set_region(hose->regions + 1, 241 CFG_PCI1_MEM_BASE, 242 CFG_PCI1_MEM_PHYS, 243 CFG_PCI1_MEM_SIZE, 244 PCI_REGION_MEM); 245 246 /* outbound io */ 247 pci_set_region(hose->regions + 2, 248 CFG_PCI1_IO_BASE, 249 CFG_PCI1_IO_PHYS, 250 CFG_PCI1_IO_SIZE, 251 PCI_REGION_IO); 252 253 hose->region_count = 3; 254 255 hose->first_busno=first_free_busno; 256 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 257 258 fsl_pci_init(hose); 259 260 first_free_busno=hose->last_busno+1; 261 printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", 262 hose->first_busno,hose->last_busno); 263 264 /* 265 * Activate ULI1575 legacy chip by performing a fake 266 * memory access. Needed to make ULI RTC work. 267 */ 268 in_be32((unsigned *) ((char *)(CFG_PCI1_MEM_BASE 269 + CFG_PCI1_MEM_SIZE - 0x1000000))); 270 271 } else { 272 puts("PCI-EXPRESS 1: Disabled\n"); 273 } 274 } 275 #else 276 puts("PCI-EXPRESS1: Disabled\n"); 277 #endif /* CONFIG_PCI1 */ 278 279 #ifdef CONFIG_PCI2 280 { 281 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR; 282 extern void fsl_pci_init(struct pci_controller *hose); 283 struct pci_controller *hose = &pci2_hose; 284 285 286 /* inbound */ 287 pci_set_region(hose->regions + 0, 288 CFG_PCI_MEMORY_BUS, 289 CFG_PCI_MEMORY_PHYS, 290 CFG_PCI_MEMORY_SIZE, 291 PCI_REGION_MEM | PCI_REGION_MEMORY); 292 293 /* outbound memory */ 294 pci_set_region(hose->regions + 1, 295 CFG_PCI2_MEM_BASE, 296 CFG_PCI2_MEM_PHYS, 297 CFG_PCI2_MEM_SIZE, 298 PCI_REGION_MEM); 299 300 /* outbound io */ 301 pci_set_region(hose->regions + 2, 302 CFG_PCI2_IO_BASE, 303 CFG_PCI2_IO_PHYS, 304 CFG_PCI2_IO_SIZE, 305 PCI_REGION_IO); 306 307 hose->region_count = 3; 308 309 hose->first_busno=first_free_busno; 310 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 311 312 fsl_pci_init(hose); 313 314 first_free_busno=hose->last_busno+1; 315 printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", 316 hose->first_busno,hose->last_busno); 317 } 318 #else 319 puts("PCI-EXPRESS 2: Disabled\n"); 320 #endif /* CONFIG_PCI2 */ 321 322 } 323 324 #if defined(CONFIG_OF_BOARD_SETUP) 325 void 326 ft_board_setup(void *blob, bd_t *bd) 327 { 328 int node, tmp[2]; 329 const char *path; 330 331 fdt_fixup_ethernet(blob, bd); 332 333 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 334 "timebase-frequency", bd->bi_busfreq / 4, 1); 335 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 336 "bus-frequency", bd->bi_busfreq, 1); 337 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 338 "clock-frequency", bd->bi_intfreq, 1); 339 do_fixup_by_prop_u32(blob, "device_type", "soc", 4, 340 "bus-frequency", bd->bi_busfreq, 1); 341 342 do_fixup_by_compat_u32(blob, "ns16550", 343 "clock-frequency", bd->bi_busfreq, 1); 344 345 fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize); 346 347 node = fdt_path_offset(blob, "/aliases"); 348 tmp[0] = 0; 349 if (node >= 0) { 350 #ifdef CONFIG_PCI1 351 path = fdt_getprop(blob, node, "pci0", NULL); 352 if (path) { 353 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; 354 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 355 } 356 #endif 357 #ifdef CONFIG_PCI2 358 path = fdt_getprop(blob, node, "pci1", NULL); 359 if (path) { 360 tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno; 361 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 362 } 363 #endif 364 } 365 } 366 #endif 367 368 369 /* 370 * get_board_sys_clk 371 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ 372 */ 373 374 unsigned long 375 get_board_sys_clk(ulong dummy) 376 { 377 u8 i, go_bit, rd_clks; 378 ulong val = 0; 379 380 go_bit = in8(PIXIS_BASE + PIXIS_VCTL); 381 go_bit &= 0x01; 382 383 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); 384 rd_clks &= 0x1C; 385 386 /* 387 * Only if both go bit and the SCLK bit in VCFGEN0 are set 388 * should we be using the AUX register. Remember, we also set the 389 * GO bit to boot from the alternate bank on the on-board flash 390 */ 391 392 if (go_bit) { 393 if (rd_clks == 0x1c) 394 i = in8(PIXIS_BASE + PIXIS_AUX); 395 else 396 i = in8(PIXIS_BASE + PIXIS_SPD); 397 } else { 398 i = in8(PIXIS_BASE + PIXIS_SPD); 399 } 400 401 i &= 0x07; 402 403 switch (i) { 404 case 0: 405 val = 33000000; 406 break; 407 case 1: 408 val = 40000000; 409 break; 410 case 2: 411 val = 50000000; 412 break; 413 case 3: 414 val = 66000000; 415 break; 416 case 4: 417 val = 83000000; 418 break; 419 case 5: 420 val = 100000000; 421 break; 422 case 6: 423 val = 134000000; 424 break; 425 case 7: 426 val = 166000000; 427 break; 428 } 429 430 return val; 431 } 432