1 /* 2 * Copyright 2006, 2007 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <pci.h> 25 #include <asm/processor.h> 26 #include <asm/immap_86xx.h> 27 #include <asm/immap_fsl_pci.h> 28 #include <spd_sdram.h> 29 #include <asm/io.h> 30 #include <libfdt.h> 31 #include <fdt_support.h> 32 33 #include "../common/pixis.h" 34 35 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 36 extern void ddr_enable_ecc(unsigned int dram_size); 37 #endif 38 39 void sdram_init(void); 40 long int fixed_sdram(void); 41 42 43 int board_early_init_f(void) 44 { 45 return 0; 46 } 47 48 int checkboard(void) 49 { 50 printf ("Board: MPC8641HPCN, System ID: 0x%02x, " 51 "System Version: 0x%02x, FPGA Version: 0x%02x\n", 52 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), 53 in8(PIXIS_BASE + PIXIS_PVER)); 54 return 0; 55 } 56 57 58 phys_size_t 59 initdram(int board_type) 60 { 61 long dram_size = 0; 62 63 #if defined(CONFIG_SPD_EEPROM) 64 dram_size = spd_sdram(); 65 #else 66 dram_size = fixed_sdram(); 67 #endif 68 69 #if defined(CFG_RAMBOOT) 70 puts(" DDR: "); 71 return dram_size; 72 #endif 73 74 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 75 /* 76 * Initialize and enable DDR ECC. 77 */ 78 ddr_enable_ecc(dram_size); 79 #endif 80 81 puts(" DDR: "); 82 return dram_size; 83 } 84 85 86 #if !defined(CONFIG_SPD_EEPROM) 87 /* 88 * Fixed sdram init -- doesn't use serial presence detect. 89 */ 90 long int 91 fixed_sdram(void) 92 { 93 #if !defined(CFG_RAMBOOT) 94 volatile immap_t *immap = (immap_t *) CFG_IMMR; 95 volatile ccsr_ddr_t *ddr = &immap->im_ddr1; 96 97 ddr->cs0_bnds = CFG_DDR_CS0_BNDS; 98 ddr->cs0_config = CFG_DDR_CS0_CONFIG; 99 ddr->timing_cfg_3 = CFG_DDR_TIMING_3; 100 ddr->timing_cfg_0 = CFG_DDR_TIMING_0; 101 ddr->timing_cfg_1 = CFG_DDR_TIMING_1; 102 ddr->timing_cfg_2 = CFG_DDR_TIMING_2; 103 ddr->sdram_mode_1 = CFG_DDR_MODE_1; 104 ddr->sdram_mode_2 = CFG_DDR_MODE_2; 105 ddr->sdram_interval = CFG_DDR_INTERVAL; 106 ddr->sdram_data_init = CFG_DDR_DATA_INIT; 107 ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; 108 ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL; 109 ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS; 110 111 #if defined (CONFIG_DDR_ECC) 112 ddr->err_disable = 0x0000008D; 113 ddr->err_sbe = 0x00ff0000; 114 #endif 115 asm("sync;isync"); 116 117 udelay(500); 118 119 #if defined (CONFIG_DDR_ECC) 120 /* Enable ECC checking */ 121 ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000); 122 #else 123 ddr->sdram_cfg_1 = CFG_DDR_CONTROL; 124 ddr->sdram_cfg_2 = CFG_DDR_CONTROL2; 125 #endif 126 asm("sync; isync"); 127 128 udelay(500); 129 #endif 130 return CFG_SDRAM_SIZE * 1024 * 1024; 131 } 132 #endif /* !defined(CONFIG_SPD_EEPROM) */ 133 134 135 #if defined(CONFIG_PCI) 136 /* 137 * Initialize PCI Devices, report devices found. 138 */ 139 140 #ifndef CONFIG_PCI_PNP 141 static struct pci_config_table pci_fsl86xxads_config_table[] = { 142 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 143 PCI_IDSEL_NUMBER, PCI_ANY_ID, 144 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 145 PCI_ENET0_MEMADDR, 146 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, 147 {} 148 }; 149 #endif 150 151 152 static struct pci_controller pci1_hose = { 153 #ifndef CONFIG_PCI_PNP 154 config_table:pci_mpc86xxcts_config_table 155 #endif 156 }; 157 #endif /* CONFIG_PCI */ 158 159 #ifdef CONFIG_PCI2 160 static struct pci_controller pci2_hose; 161 #endif /* CONFIG_PCI2 */ 162 163 int first_free_busno = 0; 164 165 166 void pci_init_board(void) 167 { 168 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; 169 volatile ccsr_gur_t *gur = &immap->im_gur; 170 uint devdisr = gur->devdisr; 171 uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) 172 >> MPC8641_PORDEVSR_IO_SEL_SHIFT; 173 174 #ifdef CONFIG_PCI1 175 { 176 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; 177 extern void fsl_pci_init(struct pci_controller *hose); 178 struct pci_controller *hose = &pci1_hose; 179 #ifdef DEBUG 180 uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA) 181 >> MPC8641_PORBMSR_HA_SHIFT; 182 uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); 183 #endif 184 if ((io_sel == 2 || io_sel == 3 || io_sel == 5 185 || io_sel == 6 || io_sel == 7 || io_sel == 0xF) 186 && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { 187 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); 188 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); 189 if (pci->pme_msg_det) { 190 pci->pme_msg_det = 0xffffffff; 191 debug(" with errors. Clearing. Now 0x%08x", 192 pci->pme_msg_det); 193 } 194 debug("\n"); 195 196 /* inbound */ 197 pci_set_region(hose->regions + 0, 198 CFG_PCI_MEMORY_BUS, 199 CFG_PCI_MEMORY_PHYS, 200 CFG_PCI_MEMORY_SIZE, 201 PCI_REGION_MEM | PCI_REGION_MEMORY); 202 203 /* outbound memory */ 204 pci_set_region(hose->regions + 1, 205 CFG_PCI1_MEM_BASE, 206 CFG_PCI1_MEM_PHYS, 207 CFG_PCI1_MEM_SIZE, 208 PCI_REGION_MEM); 209 210 /* outbound io */ 211 pci_set_region(hose->regions + 2, 212 CFG_PCI1_IO_BASE, 213 CFG_PCI1_IO_PHYS, 214 CFG_PCI1_IO_SIZE, 215 PCI_REGION_IO); 216 217 hose->region_count = 3; 218 219 hose->first_busno=first_free_busno; 220 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 221 222 fsl_pci_init(hose); 223 224 first_free_busno=hose->last_busno+1; 225 printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", 226 hose->first_busno,hose->last_busno); 227 228 /* 229 * Activate ULI1575 legacy chip by performing a fake 230 * memory access. Needed to make ULI RTC work. 231 */ 232 in_be32((unsigned *) ((char *)(CFG_PCI1_MEM_BASE 233 + CFG_PCI1_MEM_SIZE - 0x1000000))); 234 235 } else { 236 puts("PCI-EXPRESS 1: Disabled\n"); 237 } 238 } 239 #else 240 puts("PCI-EXPRESS1: Disabled\n"); 241 #endif /* CONFIG_PCI1 */ 242 243 #ifdef CONFIG_PCI2 244 { 245 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR; 246 extern void fsl_pci_init(struct pci_controller *hose); 247 struct pci_controller *hose = &pci2_hose; 248 249 250 /* inbound */ 251 pci_set_region(hose->regions + 0, 252 CFG_PCI_MEMORY_BUS, 253 CFG_PCI_MEMORY_PHYS, 254 CFG_PCI_MEMORY_SIZE, 255 PCI_REGION_MEM | PCI_REGION_MEMORY); 256 257 /* outbound memory */ 258 pci_set_region(hose->regions + 1, 259 CFG_PCI2_MEM_BASE, 260 CFG_PCI2_MEM_PHYS, 261 CFG_PCI2_MEM_SIZE, 262 PCI_REGION_MEM); 263 264 /* outbound io */ 265 pci_set_region(hose->regions + 2, 266 CFG_PCI2_IO_BASE, 267 CFG_PCI2_IO_PHYS, 268 CFG_PCI2_IO_SIZE, 269 PCI_REGION_IO); 270 271 hose->region_count = 3; 272 273 hose->first_busno=first_free_busno; 274 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 275 276 fsl_pci_init(hose); 277 278 first_free_busno=hose->last_busno+1; 279 printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", 280 hose->first_busno,hose->last_busno); 281 } 282 #else 283 puts("PCI-EXPRESS 2: Disabled\n"); 284 #endif /* CONFIG_PCI2 */ 285 286 } 287 288 289 #if defined(CONFIG_OF_BOARD_SETUP) 290 291 void 292 ft_board_setup(void *blob, bd_t *bd) 293 { 294 int node, tmp[2]; 295 const char *path; 296 297 ft_cpu_setup(blob, bd); 298 299 node = fdt_path_offset(blob, "/aliases"); 300 tmp[0] = 0; 301 if (node >= 0) { 302 #ifdef CONFIG_PCI1 303 path = fdt_getprop(blob, node, "pci0", NULL); 304 if (path) { 305 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; 306 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 307 } 308 #endif 309 #ifdef CONFIG_PCI2 310 path = fdt_getprop(blob, node, "pci1", NULL); 311 if (path) { 312 tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno; 313 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 314 } 315 #endif 316 } 317 } 318 #endif 319 320 321 /* 322 * get_board_sys_clk 323 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ 324 */ 325 326 unsigned long 327 get_board_sys_clk(ulong dummy) 328 { 329 u8 i, go_bit, rd_clks; 330 ulong val = 0; 331 332 go_bit = in8(PIXIS_BASE + PIXIS_VCTL); 333 go_bit &= 0x01; 334 335 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); 336 rd_clks &= 0x1C; 337 338 /* 339 * Only if both go bit and the SCLK bit in VCFGEN0 are set 340 * should we be using the AUX register. Remember, we also set the 341 * GO bit to boot from the alternate bank on the on-board flash 342 */ 343 344 if (go_bit) { 345 if (rd_clks == 0x1c) 346 i = in8(PIXIS_BASE + PIXIS_AUX); 347 else 348 i = in8(PIXIS_BASE + PIXIS_SPD); 349 } else { 350 i = in8(PIXIS_BASE + PIXIS_SPD); 351 } 352 353 i &= 0x07; 354 355 switch (i) { 356 case 0: 357 val = 33000000; 358 break; 359 case 1: 360 val = 40000000; 361 break; 362 case 2: 363 val = 50000000; 364 break; 365 case 3: 366 val = 66000000; 367 break; 368 case 4: 369 val = 83000000; 370 break; 371 case 5: 372 val = 100000000; 373 break; 374 case 6: 375 val = 134000000; 376 break; 377 case 7: 378 val = 166000000; 379 break; 380 } 381 382 return val; 383 } 384