1 /* 2 * Copyright 2006, 2007 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <pci.h> 25 #include <asm/processor.h> 26 #include <asm/immap_86xx.h> 27 #include <asm/immap_fsl_pci.h> 28 #include <spd.h> 29 #include <asm/io.h> 30 31 #if defined(CONFIG_OF_FLAT_TREE) 32 #include <ft_build.h> 33 extern void ft_cpu_setup(void *blob, bd_t *bd); 34 #endif 35 36 #include "../common/pixis.h" 37 38 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 39 extern void ddr_enable_ecc(unsigned int dram_size); 40 #endif 41 42 #if defined(CONFIG_SPD_EEPROM) 43 #include "spd_sdram.h" 44 #endif 45 46 void sdram_init(void); 47 long int fixed_sdram(void); 48 49 50 int board_early_init_f(void) 51 { 52 return 0; 53 } 54 55 int checkboard(void) 56 { 57 puts("Board: MPC8641HPCN\n"); 58 59 return 0; 60 } 61 62 63 long int 64 initdram(int board_type) 65 { 66 long dram_size = 0; 67 68 #if defined(CONFIG_SPD_EEPROM) 69 dram_size = spd_sdram(); 70 #else 71 dram_size = fixed_sdram(); 72 #endif 73 74 #if defined(CFG_RAMBOOT) 75 puts(" DDR: "); 76 return dram_size; 77 #endif 78 79 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 80 /* 81 * Initialize and enable DDR ECC. 82 */ 83 ddr_enable_ecc(dram_size); 84 #endif 85 86 puts(" DDR: "); 87 return dram_size; 88 } 89 90 91 #if defined(CFG_DRAM_TEST) 92 int 93 testdram(void) 94 { 95 uint *pstart = (uint *) CFG_MEMTEST_START; 96 uint *pend = (uint *) CFG_MEMTEST_END; 97 uint *p; 98 99 puts("SDRAM test phase 1:\n"); 100 for (p = pstart; p < pend; p++) 101 *p = 0xaaaaaaaa; 102 103 for (p = pstart; p < pend; p++) { 104 if (*p != 0xaaaaaaaa) { 105 printf("SDRAM test fails at: %08x\n", (uint) p); 106 return 1; 107 } 108 } 109 110 puts("SDRAM test phase 2:\n"); 111 for (p = pstart; p < pend; p++) 112 *p = 0x55555555; 113 114 for (p = pstart; p < pend; p++) { 115 if (*p != 0x55555555) { 116 printf("SDRAM test fails at: %08x\n", (uint) p); 117 return 1; 118 } 119 } 120 121 puts("SDRAM test passed.\n"); 122 return 0; 123 } 124 #endif 125 126 127 #if !defined(CONFIG_SPD_EEPROM) 128 /* 129 * Fixed sdram init -- doesn't use serial presence detect. 130 */ 131 long int 132 fixed_sdram(void) 133 { 134 #if !defined(CFG_RAMBOOT) 135 volatile immap_t *immap = (immap_t *) CFG_IMMR; 136 volatile ccsr_ddr_t *ddr = &immap->im_ddr1; 137 138 ddr->cs0_bnds = CFG_DDR_CS0_BNDS; 139 ddr->cs0_config = CFG_DDR_CS0_CONFIG; 140 ddr->ext_refrec = CFG_DDR_EXT_REFRESH; 141 ddr->timing_cfg_0 = CFG_DDR_TIMING_0; 142 ddr->timing_cfg_1 = CFG_DDR_TIMING_1; 143 ddr->timing_cfg_2 = CFG_DDR_TIMING_2; 144 ddr->sdram_mode_1 = CFG_DDR_MODE_1; 145 ddr->sdram_mode_2 = CFG_DDR_MODE_2; 146 ddr->sdram_interval = CFG_DDR_INTERVAL; 147 ddr->sdram_data_init = CFG_DDR_DATA_INIT; 148 ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; 149 ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL; 150 ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS; 151 152 #if defined (CONFIG_DDR_ECC) 153 ddr->err_disable = 0x0000008D; 154 ddr->err_sbe = 0x00ff0000; 155 #endif 156 asm("sync;isync"); 157 158 udelay(500); 159 160 #if defined (CONFIG_DDR_ECC) 161 /* Enable ECC checking */ 162 ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000); 163 #else 164 ddr->sdram_cfg_1 = CFG_DDR_CONTROL; 165 ddr->sdram_cfg_2 = CFG_DDR_CONTROL2; 166 #endif 167 asm("sync; isync"); 168 169 udelay(500); 170 #endif 171 return CFG_SDRAM_SIZE * 1024 * 1024; 172 } 173 #endif /* !defined(CONFIG_SPD_EEPROM) */ 174 175 176 #if defined(CONFIG_PCI) 177 /* 178 * Initialize PCI Devices, report devices found. 179 */ 180 181 #ifndef CONFIG_PCI_PNP 182 static struct pci_config_table pci_fsl86xxads_config_table[] = { 183 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 184 PCI_IDSEL_NUMBER, PCI_ANY_ID, 185 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 186 PCI_ENET0_MEMADDR, 187 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, 188 {} 189 }; 190 #endif 191 192 193 static struct pci_controller pci1_hose = { 194 #ifndef CONFIG_PCI_PNP 195 config_table:pci_mpc86xxcts_config_table 196 #endif 197 }; 198 #endif /* CONFIG_PCI */ 199 200 #ifdef CONFIG_PCI2 201 static struct pci_controller pci2_hose; 202 #endif /* CONFIG_PCI2 */ 203 204 int first_free_busno = 0; 205 206 207 void pci_init_board(void) 208 { 209 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; 210 volatile ccsr_gur_t *gur = &immap->im_gur; 211 uint devdisr = gur->devdisr; 212 uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; 213 214 #ifdef CONFIG_PCI1 215 { 216 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; 217 extern void fsl_pci_init(struct pci_controller *hose); 218 struct pci_controller *hose = &pci1_hose; 219 #ifdef DEBUG 220 uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; 221 uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); 222 #endif 223 if ((io_sel == 2 || io_sel == 3 || io_sel == 5 224 || io_sel == 6 || io_sel == 7 || io_sel == 0xF) 225 && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { 226 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); 227 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); 228 if (pci->pme_msg_det) { 229 pci->pme_msg_det = 0xffffffff; 230 debug(" with errors. Clearing. Now 0x%08x", 231 pci->pme_msg_det); 232 } 233 debug("\n"); 234 235 /* inbound */ 236 pci_set_region(hose->regions + 0, 237 CFG_PCI_MEMORY_BUS, 238 CFG_PCI_MEMORY_PHYS, 239 CFG_PCI_MEMORY_SIZE, 240 PCI_REGION_MEM | PCI_REGION_MEMORY); 241 242 /* outbound memory */ 243 pci_set_region(hose->regions + 1, 244 CFG_PCI1_MEM_BASE, 245 CFG_PCI1_MEM_PHYS, 246 CFG_PCI1_MEM_SIZE, 247 PCI_REGION_MEM); 248 249 /* outbound io */ 250 pci_set_region(hose->regions + 2, 251 CFG_PCI1_IO_BASE, 252 CFG_PCI1_IO_PHYS, 253 CFG_PCI1_IO_SIZE, 254 PCI_REGION_IO); 255 256 hose->region_count = 3; 257 258 hose->first_busno=first_free_busno; 259 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 260 261 fsl_pci_init(hose); 262 263 first_free_busno=hose->last_busno+1; 264 printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", 265 hose->first_busno,hose->last_busno); 266 267 /* 268 * Activate ULI1575 legacy chip by performing a fake 269 * memory access. Needed to make ULI RTC work. 270 */ 271 in_be32((unsigned *) ((char *)(CFG_PCI1_MEM_BASE 272 + CFG_PCI1_MEM_SIZE - 0x1000000))); 273 274 } else { 275 puts("PCI-EXPRESS 1: Disabled\n"); 276 } 277 } 278 #else 279 puts("PCI-EXPRESS1: Disabled\n"); 280 #endif /* CONFIG_PCI1 */ 281 282 #ifdef CONFIG_PCI2 283 { 284 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR; 285 extern void fsl_pci_init(struct pci_controller *hose); 286 struct pci_controller *hose = &pci2_hose; 287 288 289 /* inbound */ 290 pci_set_region(hose->regions + 0, 291 CFG_PCI_MEMORY_BUS, 292 CFG_PCI_MEMORY_PHYS, 293 CFG_PCI_MEMORY_SIZE, 294 PCI_REGION_MEM | PCI_REGION_MEMORY); 295 296 /* outbound memory */ 297 pci_set_region(hose->regions + 1, 298 CFG_PCI2_MEM_BASE, 299 CFG_PCI2_MEM_PHYS, 300 CFG_PCI2_MEM_SIZE, 301 PCI_REGION_MEM); 302 303 /* outbound io */ 304 pci_set_region(hose->regions + 2, 305 CFG_PCI2_IO_BASE, 306 CFG_PCI2_IO_PHYS, 307 CFG_PCI2_IO_SIZE, 308 PCI_REGION_IO); 309 310 hose->region_count = 3; 311 312 hose->first_busno=first_free_busno; 313 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 314 315 fsl_pci_init(hose); 316 317 first_free_busno=hose->last_busno+1; 318 printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", 319 hose->first_busno,hose->last_busno); 320 } 321 #else 322 puts("PCI-EXPRESS 2: Disabled\n"); 323 #endif /* CONFIG_PCI2 */ 324 325 } 326 327 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) 328 void 329 ft_board_setup(void *blob, bd_t *bd) 330 { 331 u32 *p; 332 int len; 333 334 ft_cpu_setup(blob, bd); 335 336 p = ft_get_prop(blob, "/memory/reg", &len); 337 if (p != NULL) { 338 *p++ = cpu_to_be32(bd->bi_memstart); 339 *p = cpu_to_be32(bd->bi_memsize); 340 } 341 #ifdef CONFIG_PCI1 342 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@8000/bus-range", &len); 343 if (p != NULL) { 344 p[0] = 0; 345 p[1] = pci1_hose.last_busno - pci1_hose.first_busno; 346 debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]); 347 } 348 #endif 349 #ifdef CONFIG_PCI2 350 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len); 351 if (p != NULL) { 352 p[0] = 0; 353 p[1] = pci2_hose.last_busno - pci2_hose.first_busno; 354 debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]); 355 } 356 #endif 357 } 358 #endif 359 360 361 /* 362 * get_board_sys_clk 363 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ 364 */ 365 366 unsigned long 367 get_board_sys_clk(ulong dummy) 368 { 369 u8 i, go_bit, rd_clks; 370 ulong val = 0; 371 372 go_bit = in8(PIXIS_BASE + PIXIS_VCTL); 373 go_bit &= 0x01; 374 375 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); 376 rd_clks &= 0x1C; 377 378 /* 379 * Only if both go bit and the SCLK bit in VCFGEN0 are set 380 * should we be using the AUX register. Remember, we also set the 381 * GO bit to boot from the alternate bank on the on-board flash 382 */ 383 384 if (go_bit) { 385 if (rd_clks == 0x1c) 386 i = in8(PIXIS_BASE + PIXIS_AUX); 387 else 388 i = in8(PIXIS_BASE + PIXIS_SPD); 389 } else { 390 i = in8(PIXIS_BASE + PIXIS_SPD); 391 } 392 393 i &= 0x07; 394 395 switch (i) { 396 case 0: 397 val = 33000000; 398 break; 399 case 1: 400 val = 40000000; 401 break; 402 case 2: 403 val = 50000000; 404 break; 405 case 3: 406 val = 66000000; 407 break; 408 case 4: 409 val = 83000000; 410 break; 411 case 5: 412 val = 100000000; 413 break; 414 case 6: 415 val = 134000000; 416 break; 417 case 7: 418 val = 166000000; 419 break; 420 } 421 422 return val; 423 } 424