1 /* 2 * Copyright 2008,2010 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2000 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <asm/fsl_law.h> 28 #include <asm/mmu.h> 29 30 /* 31 * LAW(Local Access Window) configuration: 32 * 33 * 0x0000_0000 0x7fff_ffff DDR 2G 34 * if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT) 35 * 0x8000_0000 0x9fff_ffff PCIE1 MEM 512M 36 * 0xa000_0000 0xbfff_ffff PCIE2 MEM 512M 37 * else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT) 38 * 0x8000_0000 0x9fff_ffff RapidIO 512M 39 * endif 40 * (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT) 41 * 0xffc0_0000 0xffc0_ffff PCIE1 IO 64K 42 * 0xffc1_0000 0xffc1_ffff PCIE2 IO 64K 43 * 0xffe0_0000 0xffef_ffff CCSRBAR 1M 44 * 0xffdf_0000 0xffe0_0000 PIXIS, CF 64K 45 * 0xef80_0000 0xefff_ffff FLASH (boot bank) 8M 46 * 47 * Notes: 48 * CCSRBAR doesn't need a configured Local Access Window. 49 * If flash is 8M at default position (last 8M), no LAW needed. 50 */ 51 52 struct law_entry law_table[] = { 53 #if !defined(CONFIG_SPD_EEPROM) 54 SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), 55 #endif 56 #ifdef CONFIG_PCI 57 SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), 58 SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), 59 SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1), 60 SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2), 61 #elif defined(CONFIG_RIO) 62 SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), 63 #endif 64 SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), 65 SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC), 66 }; 67 68 int num_law_entries = ARRAY_SIZE(law_table); 69