1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright 2008,2011 Freescale Semiconductor, Inc.
4  */
5 
6 #include <common.h>
7 
8 #include <fsl_ddr_sdram.h>
9 #include <fsl_ddr_dimm_params.h>
10 
11 struct board_specific_parameters {
12 	u32 n_ranks;
13 	u32 datarate_mhz_high;
14 	u32 clk_adjust;
15 	u32 cpo;
16 	u32 write_data_delay;
17 };
18 
19 /*
20  * This table contains all valid speeds we want to override with board
21  * specific parameters. datarate_mhz_high values need to be in ascending order
22  * for each n_ranks group.
23  */
24 const struct board_specific_parameters dimm0[] = {
25 	/*
26 	 * memory controller 0
27 	 *   num|  hi|  clk| cpo|wrdata|2T
28 	 * ranks| mhz|adjst|    | delay|
29 	 */
30 	{4,  333,    7,   7,     3},
31 	{4,  549,    7,   9,     3},
32 	{4,  650,    7,  10,     4},
33 	{2,  333,    7,   7,     3},
34 	{2,  549,    7,   9,     3},
35 	{2,  650,    7,  10,     4},
36 	{1,  333,    7,   7,     3},
37 	{1,  549,    7,   9,     3},
38 	{1,  650,    7,  10,     4},
39 	{}
40 };
41 
42 /*
43  * The two slots have slightly different timing. The center values are good
44  * for both slots. We use identical speed tables for them. In future use, if
45  * DIMMs have fewer center values that require two separated tables, copy the
46  * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
47  */
48 const struct board_specific_parameters *dimms[] = {
49 	dimm0,
50 	dimm0,
51 };
52 
53 void fsl_ddr_board_options(memctl_options_t *popts,
54 			dimm_params_t *pdimm,
55 			unsigned int ctrl_num)
56 {
57 	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
58 	unsigned int i;
59 	ulong ddr_freq;
60 
61 	if (ctrl_num > 1) {
62 		printf("Wrong parameter for controller number %d", ctrl_num);
63 		return;
64 	}
65 	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
66 		if (pdimm[i].n_ranks)
67 			break;
68 	}
69 	if (i >= CONFIG_DIMM_SLOTS_PER_CTLR)    /* no DIMM */
70 		return;
71 
72 	pbsp = dimms[ctrl_num];
73 
74 	/* Get clk_adjust, cpo, write_data_delay, according to the board ddr
75 	 * freqency and n_banks specified in board_specific_parameters table.
76 	 */
77 	ddr_freq = get_ddr_freq(0) / 1000000;
78 	while (pbsp->datarate_mhz_high) {
79 		if (pbsp->n_ranks == pdimm[i].n_ranks) {
80 			if (ddr_freq <= pbsp->datarate_mhz_high) {
81 				popts->clk_adjust = pbsp->clk_adjust;
82 				popts->cpo_override = pbsp->cpo;
83 				popts->write_data_delay =
84 					pbsp->write_data_delay;
85 				goto found;
86 			}
87 			pbsp_highest = pbsp;
88 		}
89 		pbsp++;
90 	}
91 
92 	if (pbsp_highest) {
93 		printf("Error: board specific timing not found "
94 			"for data rate %lu MT/s!\n"
95 			"Trying to use the highest speed (%u) parameters\n",
96 			ddr_freq, pbsp_highest->datarate_mhz_high);
97 		popts->clk_adjust = pbsp_highest->clk_adjust;
98 		popts->cpo_override = pbsp_highest->cpo;
99 		popts->write_data_delay = pbsp_highest->write_data_delay;
100 	} else {
101 		panic("DIMM is not supported by this board");
102 	}
103 
104 found:
105 	/* 2T timing enable */
106 	popts->twot_en = 1;
107 }
108