1 /* 2 * Copyright 2007,2009-2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/immap_86xx.h> 28 #include <asm/fsl_pci.h> 29 #include <asm/fsl_ddr_sdram.h> 30 #include <asm/fsl_serdes.h> 31 #include <i2c.h> 32 #include <asm/io.h> 33 #include <libfdt.h> 34 #include <fdt_support.h> 35 #include <spd_sdram.h> 36 #include <netdev.h> 37 38 void sdram_init(void); 39 phys_size_t fixed_sdram(void); 40 int mpc8610hpcd_diu_init(void); 41 42 43 /* called before any console output */ 44 int board_early_init_f(void) 45 { 46 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 47 volatile ccsr_gur_t *gur = &immap->im_gur; 48 49 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */ 50 51 return 0; 52 } 53 54 int misc_init_r(void) 55 { 56 u8 tmp_val, version; 57 u8 *pixis_base = (u8 *)PIXIS_BASE; 58 59 /*Do not use 8259PIC*/ 60 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); 61 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80); 62 63 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/ 64 version = in_8(pixis_base + PIXIS_PVER); 65 if(version >= 0x07) { 66 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); 67 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf); 68 } 69 70 /* Using this for DIU init before the driver in linux takes over 71 * Enable the TFP410 Encoder (I2C address 0x38) 72 */ 73 74 tmp_val = 0xBF; 75 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); 76 /* Verify if enabled */ 77 tmp_val = 0; 78 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); 79 debug("DVI Encoder Read: 0x%02lx\n",tmp_val); 80 81 tmp_val = 0x10; 82 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); 83 /* Verify if enabled */ 84 tmp_val = 0; 85 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); 86 debug("DVI Encoder Read: 0x%02lx\n",tmp_val); 87 88 return 0; 89 } 90 91 int checkboard(void) 92 { 93 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 94 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; 95 u8 *pixis_base = (u8 *)PIXIS_BASE; 96 97 printf ("Board: MPC8610HPCD, System ID: 0x%02x, " 98 "System Version: 0x%02x, FPGA Version: 0x%02x\n", 99 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 100 in_8(pixis_base + PIXIS_PVER)); 101 102 mcm->abcr |= 0x00010000; /* 0 */ 103 mcm->hpmr3 = 0x80000008; /* 4c */ 104 mcm->hpmr0 = 0; 105 mcm->hpmr1 = 0; 106 mcm->hpmr2 = 0; 107 mcm->hpmr4 = 0; 108 mcm->hpmr5 = 0; 109 110 return 0; 111 } 112 113 114 phys_size_t 115 initdram(int board_type) 116 { 117 phys_size_t dram_size = 0; 118 119 #if defined(CONFIG_SPD_EEPROM) 120 dram_size = fsl_ddr_sdram(); 121 #else 122 dram_size = fixed_sdram(); 123 #endif 124 125 setup_ddr_bat(dram_size); 126 127 puts(" DDR: "); 128 return dram_size; 129 } 130 131 132 #if !defined(CONFIG_SPD_EEPROM) 133 /* 134 * Fixed sdram init -- doesn't use serial presence detect. 135 */ 136 137 phys_size_t fixed_sdram(void) 138 { 139 #if !defined(CONFIG_SYS_RAMBOOT) 140 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 141 volatile ccsr_ddr_t *ddr = &immap->im_ddr1; 142 uint d_init; 143 144 ddr->cs0_bnds = 0x0000001f; 145 ddr->cs0_config = 0x80010202; 146 147 ddr->timing_cfg_3 = 0x00000000; 148 ddr->timing_cfg_0 = 0x00260802; 149 ddr->timing_cfg_1 = 0x3935d322; 150 ddr->timing_cfg_2 = 0x14904cc8; 151 ddr->sdram_mode = 0x00480432; 152 ddr->sdram_mode_2 = 0x00000000; 153 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */ 154 ddr->sdram_data_init = 0xDEADBEEF; 155 ddr->sdram_clk_cntl = 0x03800000; 156 ddr->sdram_cfg_2 = 0x04400010; 157 158 #if defined(CONFIG_DDR_ECC) 159 ddr->err_int_en = 0x0000000d; 160 ddr->err_disable = 0x00000000; 161 ddr->err_sbe = 0x00010000; 162 #endif 163 asm("sync;isync"); 164 165 udelay(500); 166 167 ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/ 168 169 170 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 171 d_init = 1; 172 debug("DDR - 1st controller: memory initializing\n"); 173 /* 174 * Poll until memory is initialized. 175 * 512 Meg at 400 might hit this 200 times or so. 176 */ 177 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) 178 udelay(1000); 179 180 debug("DDR: memory initialized\n\n"); 181 asm("sync; isync"); 182 udelay(500); 183 #endif 184 185 return 512 * 1024 * 1024; 186 #endif 187 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 188 } 189 190 #endif 191 192 #if defined(CONFIG_PCI) 193 /* 194 * Initialize PCI Devices, report devices found. 195 */ 196 197 #ifndef CONFIG_PCI_PNP 198 static struct pci_config_table pci_fsl86xxads_config_table[] = { 199 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 200 PCI_IDSEL_NUMBER, PCI_ANY_ID, 201 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 202 PCI_ENET0_MEMADDR, 203 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} }, 204 {} 205 }; 206 #endif 207 208 209 static struct pci_controller pci1_hose = { 210 #ifndef CONFIG_PCI_PNP 211 config_table:pci_mpc86xxcts_config_table 212 #endif 213 }; 214 #endif /* CONFIG_PCI */ 215 216 void pci_init_board(void) 217 { 218 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; 219 volatile ccsr_gur_t *gur = &immap->im_gur; 220 struct fsl_pci_info pci_info; 221 u32 devdisr, pordevsr; 222 int first_free_busno; 223 int pci_agent; 224 225 devdisr = in_be32(&gur->devdisr); 226 pordevsr = in_be32(&gur->pordevsr); 227 228 first_free_busno = fsl_pcie_init_board(0); 229 230 #ifdef CONFIG_PCI1 231 if (!(devdisr & MPC86xx_DEVDISR_PCI1)) { 232 SET_STD_PCI_INFO(pci_info, 1); 233 set_next_law(pci_info.mem_phys, 234 law_size_bits(pci_info.mem_size), pci_info.law); 235 set_next_law(pci_info.io_phys, 236 law_size_bits(pci_info.io_size), pci_info.law); 237 238 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); 239 printf("PCI: connected to PCI slots as %s" \ 240 " (base address %lx)\n", 241 pci_agent ? "Agent" : "Host", 242 pci_info.regs); 243 first_free_busno = fsl_pci_init_port(&pci_info, 244 &pci1_hose, first_free_busno); 245 } else { 246 printf("PCI: disabled\n"); 247 } 248 249 puts("\n"); 250 #else 251 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */ 252 #endif 253 254 fsl_pcie_init_board(first_free_busno); 255 } 256 257 #if defined(CONFIG_OF_BOARD_SETUP) 258 void 259 ft_board_setup(void *blob, bd_t *bd) 260 { 261 ft_cpu_setup(blob, bd); 262 263 FT_FSL_PCI_SETUP; 264 } 265 #endif 266 267 /* 268 * get_board_sys_clk 269 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ 270 */ 271 272 unsigned long 273 get_board_sys_clk(ulong dummy) 274 { 275 u8 i; 276 ulong val = 0; 277 u8 *pixis_base = (u8 *)PIXIS_BASE; 278 279 i = in_8(pixis_base + PIXIS_SPD); 280 i &= 0x07; 281 282 switch (i) { 283 case 0: 284 val = 33333000; 285 break; 286 case 1: 287 val = 39999600; 288 break; 289 case 2: 290 val = 49999500; 291 break; 292 case 3: 293 val = 66666000; 294 break; 295 case 4: 296 val = 83332500; 297 break; 298 case 5: 299 val = 99999000; 300 break; 301 case 6: 302 val = 133332000; 303 break; 304 case 7: 305 val = 166665000; 306 break; 307 } 308 309 return val; 310 } 311 312 int board_eth_init(bd_t *bis) 313 { 314 return pci_eth_init(bis); 315 } 316 317 void board_reset(void) 318 { 319 u8 *pixis_base = (u8 *)PIXIS_BASE; 320 321 out_8(pixis_base + PIXIS_RST, 0); 322 323 while (1) 324 ; 325 } 326