1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/immap_86xx.h> 28 #include <asm/fsl_pci.h> 29 #include <asm/fsl_ddr_sdram.h> 30 #include <i2c.h> 31 #include <asm/io.h> 32 #include <libfdt.h> 33 #include <fdt_support.h> 34 #include <spd_sdram.h> 35 #include <netdev.h> 36 37 #include "../common/pixis.h" 38 39 void sdram_init(void); 40 phys_size_t fixed_sdram(void); 41 void mpc8610hpcd_diu_init(void); 42 43 44 /* called before any console output */ 45 int board_early_init_f(void) 46 { 47 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 48 volatile ccsr_gur_t *gur = &immap->im_gur; 49 50 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */ 51 52 return 0; 53 } 54 55 int misc_init_r(void) 56 { 57 u8 tmp_val, version; 58 u8 *pixis_base = (u8 *)PIXIS_BASE; 59 60 /*Do not use 8259PIC*/ 61 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); 62 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80); 63 64 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/ 65 version = in_8(pixis_base + PIXIS_PVER); 66 if(version >= 0x07) { 67 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); 68 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf); 69 } 70 71 /* Using this for DIU init before the driver in linux takes over 72 * Enable the TFP410 Encoder (I2C address 0x38) 73 */ 74 75 tmp_val = 0xBF; 76 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); 77 /* Verify if enabled */ 78 tmp_val = 0; 79 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); 80 debug("DVI Encoder Read: 0x%02lx\n",tmp_val); 81 82 tmp_val = 0x10; 83 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); 84 /* Verify if enabled */ 85 tmp_val = 0; 86 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); 87 debug("DVI Encoder Read: 0x%02lx\n",tmp_val); 88 89 #ifdef CONFIG_FSL_DIU_FB 90 mpc8610hpcd_diu_init(); 91 #endif 92 93 return 0; 94 } 95 96 int checkboard(void) 97 { 98 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 99 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; 100 u8 *pixis_base = (u8 *)PIXIS_BASE; 101 102 printf ("Board: MPC8610HPCD, System ID: 0x%02x, " 103 "System Version: 0x%02x, FPGA Version: 0x%02x\n", 104 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 105 in_8(pixis_base + PIXIS_PVER)); 106 107 mcm->abcr |= 0x00010000; /* 0 */ 108 mcm->hpmr3 = 0x80000008; /* 4c */ 109 mcm->hpmr0 = 0; 110 mcm->hpmr1 = 0; 111 mcm->hpmr2 = 0; 112 mcm->hpmr4 = 0; 113 mcm->hpmr5 = 0; 114 115 return 0; 116 } 117 118 119 phys_size_t 120 initdram(int board_type) 121 { 122 phys_size_t dram_size = 0; 123 124 #if defined(CONFIG_SPD_EEPROM) 125 dram_size = fsl_ddr_sdram(); 126 #else 127 dram_size = fixed_sdram(); 128 #endif 129 130 puts(" DDR: "); 131 return dram_size; 132 } 133 134 135 #if !defined(CONFIG_SPD_EEPROM) 136 /* 137 * Fixed sdram init -- doesn't use serial presence detect. 138 */ 139 140 phys_size_t fixed_sdram(void) 141 { 142 #if !defined(CONFIG_SYS_RAMBOOT) 143 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 144 volatile ccsr_ddr_t *ddr = &immap->im_ddr1; 145 uint d_init; 146 147 ddr->cs0_bnds = 0x0000001f; 148 ddr->cs0_config = 0x80010202; 149 150 ddr->timing_cfg_3 = 0x00000000; 151 ddr->timing_cfg_0 = 0x00260802; 152 ddr->timing_cfg_1 = 0x3935d322; 153 ddr->timing_cfg_2 = 0x14904cc8; 154 ddr->sdram_mode = 0x00480432; 155 ddr->sdram_mode_2 = 0x00000000; 156 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */ 157 ddr->sdram_data_init = 0xDEADBEEF; 158 ddr->sdram_clk_cntl = 0x03800000; 159 ddr->sdram_cfg_2 = 0x04400010; 160 161 #if defined(CONFIG_DDR_ECC) 162 ddr->err_int_en = 0x0000000d; 163 ddr->err_disable = 0x00000000; 164 ddr->err_sbe = 0x00010000; 165 #endif 166 asm("sync;isync"); 167 168 udelay(500); 169 170 ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/ 171 172 173 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 174 d_init = 1; 175 debug("DDR - 1st controller: memory initializing\n"); 176 /* 177 * Poll until memory is initialized. 178 * 512 Meg at 400 might hit this 200 times or so. 179 */ 180 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) 181 udelay(1000); 182 183 debug("DDR: memory initialized\n\n"); 184 asm("sync; isync"); 185 udelay(500); 186 #endif 187 188 return 512 * 1024 * 1024; 189 #endif 190 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 191 } 192 193 #endif 194 195 #if defined(CONFIG_PCI) 196 /* 197 * Initialize PCI Devices, report devices found. 198 */ 199 200 #ifndef CONFIG_PCI_PNP 201 static struct pci_config_table pci_fsl86xxads_config_table[] = { 202 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 203 PCI_IDSEL_NUMBER, PCI_ANY_ID, 204 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 205 PCI_ENET0_MEMADDR, 206 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} }, 207 {} 208 }; 209 #endif 210 211 212 static struct pci_controller pci1_hose = { 213 #ifndef CONFIG_PCI_PNP 214 config_table:pci_mpc86xxcts_config_table 215 #endif 216 }; 217 #endif /* CONFIG_PCI */ 218 219 #ifdef CONFIG_PCIE1 220 static struct pci_controller pcie1_hose; 221 #endif 222 223 #ifdef CONFIG_PCIE2 224 static struct pci_controller pcie2_hose; 225 #endif 226 227 int first_free_busno = 0; 228 229 void pci_init_board(void) 230 { 231 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; 232 volatile ccsr_gur_t *gur = &immap->im_gur; 233 uint devdisr = gur->devdisr; 234 uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL) 235 >> MPC8610_PORDEVSR_IO_SEL_SHIFT; 236 uint host_agent = (gur->porbmsr & MPC8610_PORBMSR_HA) 237 >> MPC8610_PORBMSR_HA_SHIFT; 238 239 printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", 240 devdisr, io_sel, host_agent); 241 242 #ifdef CONFIG_PCIE1 243 { 244 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 245 struct pci_controller *hose = &pcie1_hose; 246 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 247 int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); 248 struct pci_region *r = hose->regions; 249 250 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) { 251 printf(" PCIe 1 connected to Uli as %s (base address %x)\n", 252 pcie_ep ? "End Point" : "Root Complex", 253 (uint)pci); 254 if (pci->pme_msg_det) 255 pci->pme_msg_det = 0xffffffff; 256 257 /* outbound memory */ 258 pci_set_region(r++, 259 CONFIG_SYS_PCIE1_MEM_BUS, 260 CONFIG_SYS_PCIE1_MEM_PHYS, 261 CONFIG_SYS_PCIE1_MEM_SIZE, 262 PCI_REGION_MEM); 263 264 /* outbound io */ 265 pci_set_region(r++, 266 CONFIG_SYS_PCIE1_IO_BUS, 267 CONFIG_SYS_PCIE1_IO_PHYS, 268 CONFIG_SYS_PCIE1_IO_SIZE, 269 PCI_REGION_IO); 270 271 hose->region_count = r - hose->regions; 272 273 hose->first_busno = first_free_busno; 274 275 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 276 277 first_free_busno = hose->last_busno + 1; 278 printf(" PCI-Express 1 on bus %02x - %02x\n", 279 hose->first_busno, hose->last_busno); 280 281 } else 282 puts(" PCI-Express 1: Disabled\n"); 283 } 284 #else 285 puts("PCI-Express 1: Disabled\n"); 286 #endif /* CONFIG_PCIE1 */ 287 288 289 #ifdef CONFIG_PCIE2 290 { 291 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; 292 struct pci_controller *hose = &pcie2_hose; 293 struct pci_region *r = hose->regions; 294 295 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); 296 int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); 297 298 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) { 299 printf(" PCI-Express 2 connected to slot as %s" \ 300 " (base address %x)\n", 301 pcie_ep ? "End Point" : "Root Complex", 302 (uint)pci); 303 if (pci->pme_msg_det) 304 pci->pme_msg_det = 0xffffffff; 305 306 /* outbound memory */ 307 pci_set_region(r++, 308 CONFIG_SYS_PCIE2_MEM_BUS, 309 CONFIG_SYS_PCIE2_MEM_PHYS, 310 CONFIG_SYS_PCIE2_MEM_SIZE, 311 PCI_REGION_MEM); 312 313 /* outbound io */ 314 pci_set_region(r++, 315 CONFIG_SYS_PCIE2_IO_BUS, 316 CONFIG_SYS_PCIE2_IO_PHYS, 317 CONFIG_SYS_PCIE2_IO_SIZE, 318 PCI_REGION_IO); 319 320 hose->region_count = r - hose->regions; 321 322 hose->first_busno = first_free_busno; 323 324 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 325 326 first_free_busno = hose->last_busno + 1; 327 printf(" PCI-Express 2 on bus %02x - %02x\n", 328 hose->first_busno, hose->last_busno); 329 } else 330 puts(" PCI-Express 2: Disabled\n"); 331 } 332 #else 333 puts("PCI-Express 2: Disabled\n"); 334 #endif /* CONFIG_PCIE2 */ 335 336 337 #ifdef CONFIG_PCI1 338 { 339 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; 340 struct pci_controller *hose = &pci1_hose; 341 int pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); 342 struct pci_region *r = hose->regions; 343 344 if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) { 345 printf(" PCI connected to PCI slots as %s" \ 346 " (base address %x)\n", 347 pci_agent ? "Agent" : "Host", 348 (uint)pci); 349 350 /* outbound memory */ 351 pci_set_region(r++, 352 CONFIG_SYS_PCI1_MEM_BUS, 353 CONFIG_SYS_PCI1_MEM_PHYS, 354 CONFIG_SYS_PCI1_MEM_SIZE, 355 PCI_REGION_MEM); 356 357 /* outbound io */ 358 pci_set_region(r++, 359 CONFIG_SYS_PCI1_IO_BUS, 360 CONFIG_SYS_PCI1_IO_PHYS, 361 CONFIG_SYS_PCI1_IO_SIZE, 362 PCI_REGION_IO); 363 364 hose->region_count = r - hose->regions; 365 366 hose->first_busno = first_free_busno; 367 368 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 369 370 first_free_busno = hose->last_busno + 1; 371 printf(" PCI on bus %02x - %02x\n", 372 hose->first_busno, hose->last_busno); 373 374 375 } else 376 puts(" PCI: Disabled\n"); 377 } 378 #endif /* CONFIG_PCI1 */ 379 } 380 381 #if defined(CONFIG_OF_BOARD_SETUP) 382 void 383 ft_board_setup(void *blob, bd_t *bd) 384 { 385 ft_cpu_setup(blob, bd); 386 387 #ifdef CONFIG_PCI1 388 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 389 #endif 390 #ifdef CONFIG_PCIE1 391 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); 392 #endif 393 #ifdef CONFIG_PCIE2 394 ft_fsl_pci_setup(blob, "pci2", &pcie2_hose); 395 #endif 396 } 397 #endif 398 399 /* 400 * get_board_sys_clk 401 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ 402 */ 403 404 unsigned long 405 get_board_sys_clk(ulong dummy) 406 { 407 u8 i; 408 ulong val = 0; 409 u8 *pixis_base = (u8 *)PIXIS_BASE; 410 411 i = in_8(pixis_base + PIXIS_SPD); 412 i &= 0x07; 413 414 switch (i) { 415 case 0: 416 val = 33333000; 417 break; 418 case 1: 419 val = 39999600; 420 break; 421 case 2: 422 val = 49999500; 423 break; 424 case 3: 425 val = 66666000; 426 break; 427 case 4: 428 val = 83332500; 429 break; 430 case 5: 431 val = 99999000; 432 break; 433 case 6: 434 val = 133332000; 435 break; 436 case 7: 437 val = 166665000; 438 break; 439 } 440 441 return val; 442 } 443 444 int board_eth_init(bd_t *bis) 445 { 446 return pci_eth_init(bis); 447 } 448 449 void board_reset(void) 450 { 451 u8 *pixis_base = (u8 *)PIXIS_BASE; 452 453 out_8(pixis_base + PIXIS_RST, 0); 454 455 while (1) 456 ; 457 } 458