1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/immap_86xx.h> 28 #include <asm/immap_fsl_pci.h> 29 #include <i2c.h> 30 #include <asm/io.h> 31 #include <libfdt.h> 32 #include <fdt_support.h> 33 #include <spd_sdram.h> 34 35 #include "../common/pixis.h" 36 37 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 38 extern void ddr_enable_ecc(unsigned int dram_size); 39 #endif 40 41 void sdram_init(void); 42 long int fixed_sdram(void); 43 void mpc8610hpcd_diu_init(void); 44 45 46 /* called before any console output */ 47 int board_early_init_f(void) 48 { 49 volatile immap_t *immap = (immap_t *)CFG_IMMR; 50 volatile ccsr_gur_t *gur = &immap->im_gur; 51 52 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */ 53 54 return 0; 55 } 56 57 int misc_init_r(void) 58 { 59 u8 tmp_val, version; 60 61 /*Do not use 8259PIC*/ 62 tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0); 63 out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x80); 64 65 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/ 66 version = in8(PIXIS_BASE + PIXIS_PVER); 67 if(version >= 0x07) { 68 tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0); 69 out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xbf); 70 } 71 72 /* Using this for DIU init before the driver in linux takes over 73 * Enable the TFP410 Encoder (I2C address 0x38) 74 */ 75 76 tmp_val = 0xBF; 77 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); 78 /* Verify if enabled */ 79 tmp_val = 0; 80 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); 81 debug("DVI Encoder Read: 0x%02lx\n",tmp_val); 82 83 tmp_val = 0x10; 84 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); 85 /* Verify if enabled */ 86 tmp_val = 0; 87 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); 88 debug("DVI Encoder Read: 0x%02lx\n",tmp_val); 89 90 #ifdef CONFIG_FSL_DIU_FB 91 mpc8610hpcd_diu_init(); 92 #endif 93 94 return 0; 95 } 96 97 int checkboard(void) 98 { 99 volatile immap_t *immap = (immap_t *)CFG_IMMR; 100 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; 101 102 puts("Board: MPC8610HPCD\n"); 103 104 mcm->abcr |= 0x00010000; /* 0 */ 105 mcm->hpmr3 = 0x80000008; /* 4c */ 106 mcm->hpmr0 = 0; 107 mcm->hpmr1 = 0; 108 mcm->hpmr2 = 0; 109 mcm->hpmr4 = 0; 110 mcm->hpmr5 = 0; 111 112 return 0; 113 } 114 115 116 long int 117 initdram(int board_type) 118 { 119 long dram_size = 0; 120 121 #if defined(CONFIG_SPD_EEPROM) 122 dram_size = spd_sdram(); 123 #else 124 dram_size = fixed_sdram(); 125 #endif 126 127 #if defined(CFG_RAMBOOT) 128 puts(" DDR: "); 129 return dram_size; 130 #endif 131 132 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 133 /* 134 * Initialize and enable DDR ECC. 135 */ 136 ddr_enable_ecc(dram_size); 137 #endif 138 139 puts(" DDR: "); 140 return dram_size; 141 } 142 143 144 #if defined(CFG_DRAM_TEST) 145 int 146 testdram(void) 147 { 148 uint *pstart = (uint *) CFG_MEMTEST_START; 149 uint *pend = (uint *) CFG_MEMTEST_END; 150 uint *p; 151 152 puts("SDRAM test phase 1:\n"); 153 for (p = pstart; p < pend; p++) 154 *p = 0xaaaaaaaa; 155 156 for (p = pstart; p < pend; p++) { 157 if (*p != 0xaaaaaaaa) { 158 printf("SDRAM test fails at: %08x\n", (uint) p); 159 return 1; 160 } 161 } 162 163 puts("SDRAM test phase 2:\n"); 164 for (p = pstart; p < pend; p++) 165 *p = 0x55555555; 166 167 for (p = pstart; p < pend; p++) { 168 if (*p != 0x55555555) { 169 printf("SDRAM test fails at: %08x\n", (uint) p); 170 return 1; 171 } 172 } 173 174 puts("SDRAM test passed.\n"); 175 return 0; 176 } 177 #endif 178 179 180 #if !defined(CONFIG_SPD_EEPROM) 181 /* 182 * Fixed sdram init -- doesn't use serial presence detect. 183 */ 184 185 long int fixed_sdram(void) 186 { 187 #if !defined(CFG_RAMBOOT) 188 volatile immap_t *immap = (immap_t *)CFG_IMMR; 189 volatile ccsr_ddr_t *ddr = &immap->im_ddr1; 190 uint d_init; 191 192 ddr->cs0_bnds = 0x0000001f; 193 ddr->cs0_config = 0x80010202; 194 195 ddr->ext_refrec = 0x00000000; 196 ddr->timing_cfg_0 = 0x00260802; 197 ddr->timing_cfg_1 = 0x3935d322; 198 ddr->timing_cfg_2 = 0x14904cc8; 199 ddr->sdram_mode_1 = 0x00480432; 200 ddr->sdram_mode_2 = 0x00000000; 201 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */ 202 ddr->sdram_data_init = 0xDEADBEEF; 203 ddr->sdram_clk_cntl = 0x03800000; 204 ddr->sdram_cfg_2 = 0x04400010; 205 206 #if defined(CONFIG_DDR_ECC) 207 ddr->err_int_en = 0x0000000d; 208 ddr->err_disable = 0x00000000; 209 ddr->err_sbe = 0x00010000; 210 #endif 211 asm("sync;isync"); 212 213 udelay(500); 214 215 ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/ 216 217 218 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 219 d_init = 1; 220 debug("DDR - 1st controller: memory initializing\n"); 221 /* 222 * Poll until memory is initialized. 223 * 512 Meg at 400 might hit this 200 times or so. 224 */ 225 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) 226 udelay(1000); 227 228 debug("DDR: memory initialized\n\n"); 229 asm("sync; isync"); 230 udelay(500); 231 #endif 232 233 return 512 * 1024 * 1024; 234 #endif 235 return CFG_SDRAM_SIZE * 1024 * 1024; 236 } 237 238 #endif 239 240 #if defined(CONFIG_PCI) 241 /* 242 * Initialize PCI Devices, report devices found. 243 */ 244 245 #ifndef CONFIG_PCI_PNP 246 static struct pci_config_table pci_fsl86xxads_config_table[] = { 247 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 248 PCI_IDSEL_NUMBER, PCI_ANY_ID, 249 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 250 PCI_ENET0_MEMADDR, 251 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} }, 252 {} 253 }; 254 #endif 255 256 257 static struct pci_controller pci1_hose = { 258 #ifndef CONFIG_PCI_PNP 259 config_table:pci_mpc86xxcts_config_table 260 #endif 261 }; 262 #endif /* CONFIG_PCI */ 263 264 #ifdef CONFIG_PCIE1 265 static struct pci_controller pcie1_hose; 266 #endif 267 268 #ifdef CONFIG_PCIE2 269 static struct pci_controller pcie2_hose; 270 #endif 271 272 int first_free_busno = 0; 273 274 void pci_init_board(void) 275 { 276 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; 277 volatile ccsr_gur_t *gur = &immap->im_gur; 278 uint devdisr = gur->devdisr; 279 uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL) 280 >> MPC8610_PORDEVSR_IO_SEL_SHIFT; 281 uint host_agent = (gur->porbmsr & MPC8610_PORBMSR_HA) 282 >> MPC8610_PORBMSR_HA_SHIFT; 283 284 printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", 285 devdisr, io_sel, host_agent); 286 287 #ifdef CONFIG_PCIE1 288 { 289 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; 290 extern void fsl_pci_init(struct pci_controller *hose); 291 struct pci_controller *hose = &pcie1_hose; 292 int pcie_configured = (io_sel == 1) || (io_sel == 4); 293 int pcie_ep = (host_agent == 0) || (host_agent == 2) || 294 (host_agent == 5); 295 296 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) { 297 printf(" PCIe 1 connected to Uli as %s (base address %x)\n", 298 pcie_ep ? "End Point" : "Root Complex", 299 (uint)pci); 300 if (pci->pme_msg_det) 301 pci->pme_msg_det = 0xffffffff; 302 303 /* inbound */ 304 pci_set_region(hose->regions + 0, 305 CFG_PCI_MEMORY_BUS, 306 CFG_PCI_MEMORY_PHYS, 307 CFG_PCI_MEMORY_SIZE, 308 PCI_REGION_MEM | PCI_REGION_MEMORY); 309 310 /* outbound memory */ 311 pci_set_region(hose->regions + 1, 312 CFG_PCIE1_MEM_BASE, 313 CFG_PCIE1_MEM_PHYS, 314 CFG_PCIE1_MEM_SIZE, 315 PCI_REGION_MEM); 316 317 /* outbound io */ 318 pci_set_region(hose->regions + 2, 319 CFG_PCIE1_IO_BASE, 320 CFG_PCIE1_IO_PHYS, 321 CFG_PCIE1_IO_SIZE, 322 PCI_REGION_IO); 323 324 hose->region_count = 3; 325 326 hose->first_busno = first_free_busno; 327 pci_setup_indirect(hose, (int)&pci->cfg_addr, 328 (int)&pci->cfg_data); 329 330 fsl_pci_init(hose); 331 332 first_free_busno = hose->last_busno + 1; 333 printf(" PCI-Express 1 on bus %02x - %02x\n", 334 hose->first_busno, hose->last_busno); 335 336 } else 337 puts(" PCI-Express 1: Disabled\n"); 338 } 339 #else 340 puts("PCI-Express 1: Disabled\n"); 341 #endif /* CONFIG_PCIE1 */ 342 343 344 #ifdef CONFIG_PCIE2 345 { 346 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR; 347 extern void fsl_pci_init(struct pci_controller *hose); 348 struct pci_controller *hose = &pcie2_hose; 349 350 int pcie_configured = (io_sel == 0) || (io_sel == 4); 351 int pcie_ep = (host_agent == 0) || (host_agent == 1) || 352 (host_agent == 4); 353 354 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) { 355 printf(" PCI-Express 2 connected to slot as %s" \ 356 " (base address %x)\n", 357 pcie_ep ? "End Point" : "Root Complex", 358 (uint)pci); 359 if (pci->pme_msg_det) 360 pci->pme_msg_det = 0xffffffff; 361 362 /* inbound */ 363 pci_set_region(hose->regions + 0, 364 CFG_PCI_MEMORY_BUS, 365 CFG_PCI_MEMORY_PHYS, 366 CFG_PCI_MEMORY_SIZE, 367 PCI_REGION_MEM | PCI_REGION_MEMORY); 368 369 /* outbound memory */ 370 pci_set_region(hose->regions + 1, 371 CFG_PCIE2_MEM_BASE, 372 CFG_PCIE2_MEM_PHYS, 373 CFG_PCIE2_MEM_SIZE, 374 PCI_REGION_MEM); 375 376 /* outbound io */ 377 pci_set_region(hose->regions + 2, 378 CFG_PCIE2_IO_BASE, 379 CFG_PCIE2_IO_PHYS, 380 CFG_PCIE2_IO_SIZE, 381 PCI_REGION_IO); 382 383 hose->region_count = 3; 384 385 hose->first_busno = first_free_busno; 386 pci_setup_indirect(hose, (int)&pci->cfg_addr, 387 (int)&pci->cfg_data); 388 389 fsl_pci_init(hose); 390 391 first_free_busno = hose->last_busno + 1; 392 printf(" PCI-Express 2 on bus %02x - %02x\n", 393 hose->first_busno, hose->last_busno); 394 } else 395 puts(" PCI-Express 2: Disabled\n"); 396 } 397 #else 398 puts("PCI-Express 2: Disabled\n"); 399 #endif /* CONFIG_PCIE2 */ 400 401 402 #ifdef CONFIG_PCI1 403 { 404 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; 405 extern void fsl_pci_init(struct pci_controller *hose); 406 struct pci_controller *hose = &pci1_hose; 407 int pci_agent = (host_agent >= 4) && (host_agent <= 6); 408 409 if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) { 410 printf(" PCI connected to PCI slots as %s" \ 411 " (base address %x)\n", 412 pci_agent ? "Agent" : "Host", 413 (uint)pci); 414 415 /* inbound */ 416 pci_set_region(hose->regions + 0, 417 CFG_PCI_MEMORY_BUS, 418 CFG_PCI_MEMORY_PHYS, 419 CFG_PCI_MEMORY_SIZE, 420 PCI_REGION_MEM | PCI_REGION_MEMORY); 421 422 /* outbound memory */ 423 pci_set_region(hose->regions + 1, 424 CFG_PCI1_MEM_BASE, 425 CFG_PCI1_MEM_PHYS, 426 CFG_PCI1_MEM_SIZE, 427 PCI_REGION_MEM); 428 429 /* outbound io */ 430 pci_set_region(hose->regions + 2, 431 CFG_PCI1_IO_BASE, 432 CFG_PCI1_IO_PHYS, 433 CFG_PCI1_IO_SIZE, 434 PCI_REGION_IO); 435 436 hose->region_count = 3; 437 438 hose->first_busno = first_free_busno; 439 pci_setup_indirect(hose, (int) &pci->cfg_addr, 440 (int) &pci->cfg_data); 441 442 fsl_pci_init(hose); 443 444 first_free_busno = hose->last_busno + 1; 445 printf(" PCI on bus %02x - %02x\n", 446 hose->first_busno, hose->last_busno); 447 448 449 } else 450 puts(" PCI: Disabled\n"); 451 } 452 #endif /* CONFIG_PCI1 */ 453 } 454 455 #if defined(CONFIG_OF_BOARD_SETUP) 456 void 457 ft_board_setup(void *blob, bd_t *bd) 458 { 459 int node, tmp[2]; 460 const char *path; 461 462 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 463 "timebase-frequency", bd->bi_busfreq / 4, 1); 464 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 465 "bus-frequency", bd->bi_busfreq, 1); 466 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 467 "clock-frequency", bd->bi_intfreq, 1); 468 do_fixup_by_prop_u32(blob, "device_type", "soc", 4, 469 "bus-frequency", bd->bi_busfreq, 1); 470 471 do_fixup_by_compat_u32(blob, "ns16550", 472 "clock-frequency", bd->bi_busfreq, 1); 473 474 fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize); 475 476 477 node = fdt_path_offset(blob, "/aliases"); 478 tmp[0] = 0; 479 if (node >= 0) { 480 481 #ifdef CONFIG_PCI1 482 path = fdt_getprop(blob, node, "pci0", NULL); 483 if (path) { 484 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; 485 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 486 } 487 488 #endif 489 #ifdef CONFIG_PCIE1 490 path = fdt_getprop(blob, node, "pci1", NULL); 491 if (path) { 492 tmp[1] = pcie1_hose.last_busno 493 - pcie1_hose.first_busno; 494 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 495 } 496 #endif 497 #ifdef CONFIG_PCIE2 498 path = fdt_getprop(blob, node, "pci2", NULL); 499 if (path) { 500 tmp[1] = pcie2_hose.last_busno 501 - pcie2_hose.first_busno; 502 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 503 } 504 #endif 505 } 506 } 507 #endif 508 509 /* 510 * get_board_sys_clk 511 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ 512 */ 513 514 unsigned long 515 get_board_sys_clk(ulong dummy) 516 { 517 u8 i; 518 ulong val = 0; 519 ulong a; 520 521 a = PIXIS_BASE + PIXIS_SPD; 522 i = in8(a); 523 i &= 0x07; 524 525 switch (i) { 526 case 0: 527 val = 33333000; 528 break; 529 case 1: 530 val = 39999600; 531 break; 532 case 2: 533 val = 49999500; 534 break; 535 case 3: 536 val = 66666000; 537 break; 538 case 4: 539 val = 83332500; 540 break; 541 case 5: 542 val = 99999000; 543 break; 544 case 6: 545 val = 133332000; 546 break; 547 case 7: 548 val = 166665000; 549 break; 550 } 551 552 return val; 553 } 554