1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/immap_86xx.h> 28 #include <asm/fsl_pci.h> 29 #include <asm/fsl_ddr_sdram.h> 30 #include <i2c.h> 31 #include <asm/io.h> 32 #include <libfdt.h> 33 #include <fdt_support.h> 34 #include <spd_sdram.h> 35 #include <netdev.h> 36 37 #include "../common/pixis.h" 38 39 void sdram_init(void); 40 phys_size_t fixed_sdram(void); 41 void mpc8610hpcd_diu_init(void); 42 43 44 /* called before any console output */ 45 int board_early_init_f(void) 46 { 47 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 48 volatile ccsr_gur_t *gur = &immap->im_gur; 49 50 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */ 51 52 return 0; 53 } 54 55 int misc_init_r(void) 56 { 57 u8 tmp_val, version; 58 u8 *pixis_base = (u8 *)PIXIS_BASE; 59 60 /*Do not use 8259PIC*/ 61 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); 62 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80); 63 64 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/ 65 version = in_8(pixis_base + PIXIS_PVER); 66 if(version >= 0x07) { 67 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); 68 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf); 69 } 70 71 /* Using this for DIU init before the driver in linux takes over 72 * Enable the TFP410 Encoder (I2C address 0x38) 73 */ 74 75 tmp_val = 0xBF; 76 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); 77 /* Verify if enabled */ 78 tmp_val = 0; 79 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); 80 debug("DVI Encoder Read: 0x%02lx\n",tmp_val); 81 82 tmp_val = 0x10; 83 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); 84 /* Verify if enabled */ 85 tmp_val = 0; 86 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); 87 debug("DVI Encoder Read: 0x%02lx\n",tmp_val); 88 89 #ifdef CONFIG_FSL_DIU_FB 90 mpc8610hpcd_diu_init(); 91 #endif 92 93 return 0; 94 } 95 96 int checkboard(void) 97 { 98 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 99 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; 100 u8 *pixis_base = (u8 *)PIXIS_BASE; 101 102 printf ("Board: MPC8610HPCD, System ID: 0x%02x, " 103 "System Version: 0x%02x, FPGA Version: 0x%02x\n", 104 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 105 in_8(pixis_base + PIXIS_PVER)); 106 107 mcm->abcr |= 0x00010000; /* 0 */ 108 mcm->hpmr3 = 0x80000008; /* 4c */ 109 mcm->hpmr0 = 0; 110 mcm->hpmr1 = 0; 111 mcm->hpmr2 = 0; 112 mcm->hpmr4 = 0; 113 mcm->hpmr5 = 0; 114 115 return 0; 116 } 117 118 119 phys_size_t 120 initdram(int board_type) 121 { 122 phys_size_t dram_size = 0; 123 124 #if defined(CONFIG_SPD_EEPROM) 125 dram_size = fsl_ddr_sdram(); 126 #else 127 dram_size = fixed_sdram(); 128 #endif 129 130 #if defined(CONFIG_SYS_RAMBOOT) 131 puts(" DDR: "); 132 return dram_size; 133 #endif 134 135 puts(" DDR: "); 136 return dram_size; 137 } 138 139 140 #if !defined(CONFIG_SPD_EEPROM) 141 /* 142 * Fixed sdram init -- doesn't use serial presence detect. 143 */ 144 145 phys_size_t fixed_sdram(void) 146 { 147 #if !defined(CONFIG_SYS_RAMBOOT) 148 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 149 volatile ccsr_ddr_t *ddr = &immap->im_ddr1; 150 uint d_init; 151 152 ddr->cs0_bnds = 0x0000001f; 153 ddr->cs0_config = 0x80010202; 154 155 ddr->timing_cfg_3 = 0x00000000; 156 ddr->timing_cfg_0 = 0x00260802; 157 ddr->timing_cfg_1 = 0x3935d322; 158 ddr->timing_cfg_2 = 0x14904cc8; 159 ddr->sdram_mode = 0x00480432; 160 ddr->sdram_mode_2 = 0x00000000; 161 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */ 162 ddr->sdram_data_init = 0xDEADBEEF; 163 ddr->sdram_clk_cntl = 0x03800000; 164 ddr->sdram_cfg_2 = 0x04400010; 165 166 #if defined(CONFIG_DDR_ECC) 167 ddr->err_int_en = 0x0000000d; 168 ddr->err_disable = 0x00000000; 169 ddr->err_sbe = 0x00010000; 170 #endif 171 asm("sync;isync"); 172 173 udelay(500); 174 175 ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/ 176 177 178 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 179 d_init = 1; 180 debug("DDR - 1st controller: memory initializing\n"); 181 /* 182 * Poll until memory is initialized. 183 * 512 Meg at 400 might hit this 200 times or so. 184 */ 185 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) 186 udelay(1000); 187 188 debug("DDR: memory initialized\n\n"); 189 asm("sync; isync"); 190 udelay(500); 191 #endif 192 193 return 512 * 1024 * 1024; 194 #endif 195 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 196 } 197 198 #endif 199 200 #if defined(CONFIG_PCI) 201 /* 202 * Initialize PCI Devices, report devices found. 203 */ 204 205 #ifndef CONFIG_PCI_PNP 206 static struct pci_config_table pci_fsl86xxads_config_table[] = { 207 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 208 PCI_IDSEL_NUMBER, PCI_ANY_ID, 209 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 210 PCI_ENET0_MEMADDR, 211 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} }, 212 {} 213 }; 214 #endif 215 216 217 static struct pci_controller pci1_hose = { 218 #ifndef CONFIG_PCI_PNP 219 config_table:pci_mpc86xxcts_config_table 220 #endif 221 }; 222 #endif /* CONFIG_PCI */ 223 224 #ifdef CONFIG_PCIE1 225 static struct pci_controller pcie1_hose; 226 #endif 227 228 #ifdef CONFIG_PCIE2 229 static struct pci_controller pcie2_hose; 230 #endif 231 232 int first_free_busno = 0; 233 234 void pci_init_board(void) 235 { 236 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; 237 volatile ccsr_gur_t *gur = &immap->im_gur; 238 uint devdisr = gur->devdisr; 239 uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL) 240 >> MPC8610_PORDEVSR_IO_SEL_SHIFT; 241 uint host_agent = (gur->porbmsr & MPC8610_PORBMSR_HA) 242 >> MPC8610_PORBMSR_HA_SHIFT; 243 244 printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", 245 devdisr, io_sel, host_agent); 246 247 #ifdef CONFIG_PCIE1 248 { 249 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 250 struct pci_controller *hose = &pcie1_hose; 251 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 252 int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); 253 struct pci_region *r = hose->regions; 254 255 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) { 256 printf(" PCIe 1 connected to Uli as %s (base address %x)\n", 257 pcie_ep ? "End Point" : "Root Complex", 258 (uint)pci); 259 if (pci->pme_msg_det) 260 pci->pme_msg_det = 0xffffffff; 261 262 /* outbound memory */ 263 pci_set_region(r++, 264 CONFIG_SYS_PCIE1_MEM_BUS, 265 CONFIG_SYS_PCIE1_MEM_PHYS, 266 CONFIG_SYS_PCIE1_MEM_SIZE, 267 PCI_REGION_MEM); 268 269 /* outbound io */ 270 pci_set_region(r++, 271 CONFIG_SYS_PCIE1_IO_BUS, 272 CONFIG_SYS_PCIE1_IO_PHYS, 273 CONFIG_SYS_PCIE1_IO_SIZE, 274 PCI_REGION_IO); 275 276 hose->region_count = r - hose->regions; 277 278 hose->first_busno = first_free_busno; 279 280 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 281 282 first_free_busno = hose->last_busno + 1; 283 printf(" PCI-Express 1 on bus %02x - %02x\n", 284 hose->first_busno, hose->last_busno); 285 286 } else 287 puts(" PCI-Express 1: Disabled\n"); 288 } 289 #else 290 puts("PCI-Express 1: Disabled\n"); 291 #endif /* CONFIG_PCIE1 */ 292 293 294 #ifdef CONFIG_PCIE2 295 { 296 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; 297 struct pci_controller *hose = &pcie2_hose; 298 struct pci_region *r = hose->regions; 299 300 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); 301 int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); 302 303 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) { 304 printf(" PCI-Express 2 connected to slot as %s" \ 305 " (base address %x)\n", 306 pcie_ep ? "End Point" : "Root Complex", 307 (uint)pci); 308 if (pci->pme_msg_det) 309 pci->pme_msg_det = 0xffffffff; 310 311 /* outbound memory */ 312 pci_set_region(r++, 313 CONFIG_SYS_PCIE2_MEM_BUS, 314 CONFIG_SYS_PCIE2_MEM_PHYS, 315 CONFIG_SYS_PCIE2_MEM_SIZE, 316 PCI_REGION_MEM); 317 318 /* outbound io */ 319 pci_set_region(r++, 320 CONFIG_SYS_PCIE2_IO_BUS, 321 CONFIG_SYS_PCIE2_IO_PHYS, 322 CONFIG_SYS_PCIE2_IO_SIZE, 323 PCI_REGION_IO); 324 325 hose->region_count = r - hose->regions; 326 327 hose->first_busno = first_free_busno; 328 329 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 330 331 first_free_busno = hose->last_busno + 1; 332 printf(" PCI-Express 2 on bus %02x - %02x\n", 333 hose->first_busno, hose->last_busno); 334 } else 335 puts(" PCI-Express 2: Disabled\n"); 336 } 337 #else 338 puts("PCI-Express 2: Disabled\n"); 339 #endif /* CONFIG_PCIE2 */ 340 341 342 #ifdef CONFIG_PCI1 343 { 344 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; 345 struct pci_controller *hose = &pci1_hose; 346 int pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); 347 struct pci_region *r = hose->regions; 348 349 if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) { 350 printf(" PCI connected to PCI slots as %s" \ 351 " (base address %x)\n", 352 pci_agent ? "Agent" : "Host", 353 (uint)pci); 354 355 /* outbound memory */ 356 pci_set_region(r++, 357 CONFIG_SYS_PCI1_MEM_BUS, 358 CONFIG_SYS_PCI1_MEM_PHYS, 359 CONFIG_SYS_PCI1_MEM_SIZE, 360 PCI_REGION_MEM); 361 362 /* outbound io */ 363 pci_set_region(r++, 364 CONFIG_SYS_PCI1_IO_BUS, 365 CONFIG_SYS_PCI1_IO_PHYS, 366 CONFIG_SYS_PCI1_IO_SIZE, 367 PCI_REGION_IO); 368 369 hose->region_count = r - hose->regions; 370 371 hose->first_busno = first_free_busno; 372 373 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 374 375 first_free_busno = hose->last_busno + 1; 376 printf(" PCI on bus %02x - %02x\n", 377 hose->first_busno, hose->last_busno); 378 379 380 } else 381 puts(" PCI: Disabled\n"); 382 } 383 #endif /* CONFIG_PCI1 */ 384 } 385 386 #if defined(CONFIG_OF_BOARD_SETUP) 387 void 388 ft_board_setup(void *blob, bd_t *bd) 389 { 390 ft_cpu_setup(blob, bd); 391 392 #ifdef CONFIG_PCI1 393 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 394 #endif 395 #ifdef CONFIG_PCIE1 396 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); 397 #endif 398 #ifdef CONFIG_PCIE2 399 ft_fsl_pci_setup(blob, "pci2", &pcie2_hose); 400 #endif 401 } 402 #endif 403 404 /* 405 * get_board_sys_clk 406 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ 407 */ 408 409 unsigned long 410 get_board_sys_clk(ulong dummy) 411 { 412 u8 i; 413 ulong val = 0; 414 u8 *pixis_base = (u8 *)PIXIS_BASE; 415 416 i = in_8(pixis_base + PIXIS_SPD); 417 i &= 0x07; 418 419 switch (i) { 420 case 0: 421 val = 33333000; 422 break; 423 case 1: 424 val = 39999600; 425 break; 426 case 2: 427 val = 49999500; 428 break; 429 case 3: 430 val = 66666000; 431 break; 432 case 4: 433 val = 83332500; 434 break; 435 case 5: 436 val = 99999000; 437 break; 438 case 6: 439 val = 133332000; 440 break; 441 case 7: 442 val = 166665000; 443 break; 444 } 445 446 return val; 447 } 448 449 int board_eth_init(bd_t *bis) 450 { 451 return pci_eth_init(bis); 452 } 453 454 void board_reset(void) 455 { 456 u8 *pixis_base = (u8 *)PIXIS_BASE; 457 458 out_8(pixis_base + PIXIS_RST, 0); 459 460 while (1) 461 ; 462 } 463