1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/immap_86xx.h> 28 #include <asm/immap_fsl_pci.h> 29 #include <asm/fsl_ddr_sdram.h> 30 #include <i2c.h> 31 #include <asm/io.h> 32 #include <libfdt.h> 33 #include <fdt_support.h> 34 #include <spd_sdram.h> 35 #include <netdev.h> 36 37 #include "../common/pixis.h" 38 39 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 40 extern void ddr_enable_ecc(unsigned int dram_size); 41 #endif 42 43 void sdram_init(void); 44 long int fixed_sdram(void); 45 void mpc8610hpcd_diu_init(void); 46 47 48 /* called before any console output */ 49 int board_early_init_f(void) 50 { 51 volatile immap_t *immap = (immap_t *)CFG_IMMR; 52 volatile ccsr_gur_t *gur = &immap->im_gur; 53 54 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */ 55 56 return 0; 57 } 58 59 int misc_init_r(void) 60 { 61 u8 tmp_val, version; 62 63 /*Do not use 8259PIC*/ 64 tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0); 65 out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x80); 66 67 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/ 68 version = in8(PIXIS_BASE + PIXIS_PVER); 69 if(version >= 0x07) { 70 tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0); 71 out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xbf); 72 } 73 74 /* Using this for DIU init before the driver in linux takes over 75 * Enable the TFP410 Encoder (I2C address 0x38) 76 */ 77 78 tmp_val = 0xBF; 79 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); 80 /* Verify if enabled */ 81 tmp_val = 0; 82 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); 83 debug("DVI Encoder Read: 0x%02lx\n",tmp_val); 84 85 tmp_val = 0x10; 86 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); 87 /* Verify if enabled */ 88 tmp_val = 0; 89 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); 90 debug("DVI Encoder Read: 0x%02lx\n",tmp_val); 91 92 #ifdef CONFIG_FSL_DIU_FB 93 mpc8610hpcd_diu_init(); 94 #endif 95 96 return 0; 97 } 98 99 int checkboard(void) 100 { 101 volatile immap_t *immap = (immap_t *)CFG_IMMR; 102 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; 103 104 printf ("Board: MPC8610HPCD, System ID: 0x%02x, " 105 "System Version: 0x%02x, FPGA Version: 0x%02x\n", 106 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), 107 in8(PIXIS_BASE + PIXIS_PVER)); 108 109 mcm->abcr |= 0x00010000; /* 0 */ 110 mcm->hpmr3 = 0x80000008; /* 4c */ 111 mcm->hpmr0 = 0; 112 mcm->hpmr1 = 0; 113 mcm->hpmr2 = 0; 114 mcm->hpmr4 = 0; 115 mcm->hpmr5 = 0; 116 117 return 0; 118 } 119 120 121 phys_size_t 122 initdram(int board_type) 123 { 124 long dram_size = 0; 125 126 #if defined(CONFIG_SPD_EEPROM) 127 dram_size = fsl_ddr_sdram(); 128 #else 129 dram_size = fixed_sdram(); 130 #endif 131 132 #if defined(CFG_RAMBOOT) 133 puts(" DDR: "); 134 return dram_size; 135 #endif 136 137 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 138 /* 139 * Initialize and enable DDR ECC. 140 */ 141 ddr_enable_ecc(dram_size); 142 #endif 143 144 puts(" DDR: "); 145 return dram_size; 146 } 147 148 149 #if !defined(CONFIG_SPD_EEPROM) 150 /* 151 * Fixed sdram init -- doesn't use serial presence detect. 152 */ 153 154 long int fixed_sdram(void) 155 { 156 #if !defined(CFG_RAMBOOT) 157 volatile immap_t *immap = (immap_t *)CFG_IMMR; 158 volatile ccsr_ddr_t *ddr = &immap->im_ddr1; 159 uint d_init; 160 161 ddr->cs0_bnds = 0x0000001f; 162 ddr->cs0_config = 0x80010202; 163 164 ddr->timing_cfg_3 = 0x00000000; 165 ddr->timing_cfg_0 = 0x00260802; 166 ddr->timing_cfg_1 = 0x3935d322; 167 ddr->timing_cfg_2 = 0x14904cc8; 168 ddr->sdram_mode_1 = 0x00480432; 169 ddr->sdram_mode_2 = 0x00000000; 170 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */ 171 ddr->sdram_data_init = 0xDEADBEEF; 172 ddr->sdram_clk_cntl = 0x03800000; 173 ddr->sdram_cfg_2 = 0x04400010; 174 175 #if defined(CONFIG_DDR_ECC) 176 ddr->err_int_en = 0x0000000d; 177 ddr->err_disable = 0x00000000; 178 ddr->err_sbe = 0x00010000; 179 #endif 180 asm("sync;isync"); 181 182 udelay(500); 183 184 ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/ 185 186 187 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 188 d_init = 1; 189 debug("DDR - 1st controller: memory initializing\n"); 190 /* 191 * Poll until memory is initialized. 192 * 512 Meg at 400 might hit this 200 times or so. 193 */ 194 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) 195 udelay(1000); 196 197 debug("DDR: memory initialized\n\n"); 198 asm("sync; isync"); 199 udelay(500); 200 #endif 201 202 return 512 * 1024 * 1024; 203 #endif 204 return CFG_SDRAM_SIZE * 1024 * 1024; 205 } 206 207 #endif 208 209 #if defined(CONFIG_PCI) 210 /* 211 * Initialize PCI Devices, report devices found. 212 */ 213 214 #ifndef CONFIG_PCI_PNP 215 static struct pci_config_table pci_fsl86xxads_config_table[] = { 216 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 217 PCI_IDSEL_NUMBER, PCI_ANY_ID, 218 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 219 PCI_ENET0_MEMADDR, 220 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} }, 221 {} 222 }; 223 #endif 224 225 226 static struct pci_controller pci1_hose = { 227 #ifndef CONFIG_PCI_PNP 228 config_table:pci_mpc86xxcts_config_table 229 #endif 230 }; 231 #endif /* CONFIG_PCI */ 232 233 #ifdef CONFIG_PCIE1 234 static struct pci_controller pcie1_hose; 235 #endif 236 237 #ifdef CONFIG_PCIE2 238 static struct pci_controller pcie2_hose; 239 #endif 240 241 int first_free_busno = 0; 242 243 void pci_init_board(void) 244 { 245 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; 246 volatile ccsr_gur_t *gur = &immap->im_gur; 247 uint devdisr = gur->devdisr; 248 uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL) 249 >> MPC8610_PORDEVSR_IO_SEL_SHIFT; 250 uint host_agent = (gur->porbmsr & MPC8610_PORBMSR_HA) 251 >> MPC8610_PORBMSR_HA_SHIFT; 252 253 printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", 254 devdisr, io_sel, host_agent); 255 256 #ifdef CONFIG_PCIE1 257 { 258 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; 259 extern void fsl_pci_init(struct pci_controller *hose); 260 struct pci_controller *hose = &pcie1_hose; 261 int pcie_configured = (io_sel == 1) || (io_sel == 4); 262 int pcie_ep = (host_agent == 0) || (host_agent == 2) || 263 (host_agent == 5); 264 265 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) { 266 printf(" PCIe 1 connected to Uli as %s (base address %x)\n", 267 pcie_ep ? "End Point" : "Root Complex", 268 (uint)pci); 269 if (pci->pme_msg_det) 270 pci->pme_msg_det = 0xffffffff; 271 272 /* inbound */ 273 pci_set_region(hose->regions + 0, 274 CFG_PCI_MEMORY_BUS, 275 CFG_PCI_MEMORY_PHYS, 276 CFG_PCI_MEMORY_SIZE, 277 PCI_REGION_MEM | PCI_REGION_MEMORY); 278 279 /* outbound memory */ 280 pci_set_region(hose->regions + 1, 281 CFG_PCIE1_MEM_BASE, 282 CFG_PCIE1_MEM_PHYS, 283 CFG_PCIE1_MEM_SIZE, 284 PCI_REGION_MEM); 285 286 /* outbound io */ 287 pci_set_region(hose->regions + 2, 288 CFG_PCIE1_IO_BASE, 289 CFG_PCIE1_IO_PHYS, 290 CFG_PCIE1_IO_SIZE, 291 PCI_REGION_IO); 292 293 hose->region_count = 3; 294 295 hose->first_busno = first_free_busno; 296 pci_setup_indirect(hose, (int)&pci->cfg_addr, 297 (int)&pci->cfg_data); 298 299 fsl_pci_init(hose); 300 301 first_free_busno = hose->last_busno + 1; 302 printf(" PCI-Express 1 on bus %02x - %02x\n", 303 hose->first_busno, hose->last_busno); 304 305 } else 306 puts(" PCI-Express 1: Disabled\n"); 307 } 308 #else 309 puts("PCI-Express 1: Disabled\n"); 310 #endif /* CONFIG_PCIE1 */ 311 312 313 #ifdef CONFIG_PCIE2 314 { 315 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR; 316 extern void fsl_pci_init(struct pci_controller *hose); 317 struct pci_controller *hose = &pcie2_hose; 318 319 int pcie_configured = (io_sel == 0) || (io_sel == 4); 320 int pcie_ep = (host_agent == 0) || (host_agent == 1) || 321 (host_agent == 4); 322 323 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) { 324 printf(" PCI-Express 2 connected to slot as %s" \ 325 " (base address %x)\n", 326 pcie_ep ? "End Point" : "Root Complex", 327 (uint)pci); 328 if (pci->pme_msg_det) 329 pci->pme_msg_det = 0xffffffff; 330 331 /* inbound */ 332 pci_set_region(hose->regions + 0, 333 CFG_PCI_MEMORY_BUS, 334 CFG_PCI_MEMORY_PHYS, 335 CFG_PCI_MEMORY_SIZE, 336 PCI_REGION_MEM | PCI_REGION_MEMORY); 337 338 /* outbound memory */ 339 pci_set_region(hose->regions + 1, 340 CFG_PCIE2_MEM_BASE, 341 CFG_PCIE2_MEM_PHYS, 342 CFG_PCIE2_MEM_SIZE, 343 PCI_REGION_MEM); 344 345 /* outbound io */ 346 pci_set_region(hose->regions + 2, 347 CFG_PCIE2_IO_BASE, 348 CFG_PCIE2_IO_PHYS, 349 CFG_PCIE2_IO_SIZE, 350 PCI_REGION_IO); 351 352 hose->region_count = 3; 353 354 hose->first_busno = first_free_busno; 355 pci_setup_indirect(hose, (int)&pci->cfg_addr, 356 (int)&pci->cfg_data); 357 358 fsl_pci_init(hose); 359 360 first_free_busno = hose->last_busno + 1; 361 printf(" PCI-Express 2 on bus %02x - %02x\n", 362 hose->first_busno, hose->last_busno); 363 } else 364 puts(" PCI-Express 2: Disabled\n"); 365 } 366 #else 367 puts("PCI-Express 2: Disabled\n"); 368 #endif /* CONFIG_PCIE2 */ 369 370 371 #ifdef CONFIG_PCI1 372 { 373 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; 374 extern void fsl_pci_init(struct pci_controller *hose); 375 struct pci_controller *hose = &pci1_hose; 376 int pci_agent = (host_agent >= 4) && (host_agent <= 6); 377 378 if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) { 379 printf(" PCI connected to PCI slots as %s" \ 380 " (base address %x)\n", 381 pci_agent ? "Agent" : "Host", 382 (uint)pci); 383 384 /* inbound */ 385 pci_set_region(hose->regions + 0, 386 CFG_PCI_MEMORY_BUS, 387 CFG_PCI_MEMORY_PHYS, 388 CFG_PCI_MEMORY_SIZE, 389 PCI_REGION_MEM | PCI_REGION_MEMORY); 390 391 /* outbound memory */ 392 pci_set_region(hose->regions + 1, 393 CFG_PCI1_MEM_BASE, 394 CFG_PCI1_MEM_PHYS, 395 CFG_PCI1_MEM_SIZE, 396 PCI_REGION_MEM); 397 398 /* outbound io */ 399 pci_set_region(hose->regions + 2, 400 CFG_PCI1_IO_BASE, 401 CFG_PCI1_IO_PHYS, 402 CFG_PCI1_IO_SIZE, 403 PCI_REGION_IO); 404 405 hose->region_count = 3; 406 407 hose->first_busno = first_free_busno; 408 pci_setup_indirect(hose, (int) &pci->cfg_addr, 409 (int) &pci->cfg_data); 410 411 fsl_pci_init(hose); 412 413 first_free_busno = hose->last_busno + 1; 414 printf(" PCI on bus %02x - %02x\n", 415 hose->first_busno, hose->last_busno); 416 417 418 } else 419 puts(" PCI: Disabled\n"); 420 } 421 #endif /* CONFIG_PCI1 */ 422 } 423 424 #if defined(CONFIG_OF_BOARD_SETUP) 425 void 426 ft_board_setup(void *blob, bd_t *bd) 427 { 428 int node, tmp[2]; 429 const char *path; 430 431 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 432 "timebase-frequency", bd->bi_busfreq / 4, 1); 433 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 434 "bus-frequency", bd->bi_busfreq, 1); 435 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 436 "clock-frequency", bd->bi_intfreq, 1); 437 do_fixup_by_prop_u32(blob, "device_type", "soc", 4, 438 "bus-frequency", bd->bi_busfreq, 1); 439 440 do_fixup_by_compat_u32(blob, "ns16550", 441 "clock-frequency", bd->bi_busfreq, 1); 442 443 fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize); 444 445 446 node = fdt_path_offset(blob, "/aliases"); 447 tmp[0] = 0; 448 if (node >= 0) { 449 450 #ifdef CONFIG_PCI1 451 path = fdt_getprop(blob, node, "pci0", NULL); 452 if (path) { 453 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; 454 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 455 } 456 457 #endif 458 #ifdef CONFIG_PCIE1 459 path = fdt_getprop(blob, node, "pci1", NULL); 460 if (path) { 461 tmp[1] = pcie1_hose.last_busno 462 - pcie1_hose.first_busno; 463 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 464 } 465 #endif 466 #ifdef CONFIG_PCIE2 467 path = fdt_getprop(blob, node, "pci2", NULL); 468 if (path) { 469 tmp[1] = pcie2_hose.last_busno 470 - pcie2_hose.first_busno; 471 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 472 } 473 #endif 474 } 475 } 476 #endif 477 478 /* 479 * get_board_sys_clk 480 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ 481 */ 482 483 unsigned long 484 get_board_sys_clk(ulong dummy) 485 { 486 u8 i; 487 ulong val = 0; 488 ulong a; 489 490 a = PIXIS_BASE + PIXIS_SPD; 491 i = in8(a); 492 i &= 0x07; 493 494 switch (i) { 495 case 0: 496 val = 33333000; 497 break; 498 case 1: 499 val = 39999600; 500 break; 501 case 2: 502 val = 49999500; 503 break; 504 case 3: 505 val = 66666000; 506 break; 507 case 4: 508 val = 83332500; 509 break; 510 case 5: 511 val = 99999000; 512 break; 513 case 6: 514 val = 133332000; 515 break; 516 case 7: 517 val = 166665000; 518 break; 519 } 520 521 return val; 522 } 523 524 int board_eth_init(bd_t *bis) 525 { 526 return pci_eth_init(bis); 527 } 528