1 /* 2 * Copyright 2007,2009-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <command.h> 9 #include <pci.h> 10 #include <asm/processor.h> 11 #include <asm/immap_86xx.h> 12 #include <asm/fsl_pci.h> 13 #include <fsl_ddr_sdram.h> 14 #include <asm/fsl_serdes.h> 15 #include <i2c.h> 16 #include <asm/io.h> 17 #include <libfdt.h> 18 #include <fdt_support.h> 19 #include <spd_sdram.h> 20 #include <netdev.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 void sdram_init(void); 25 phys_size_t fixed_sdram(void); 26 int mpc8610hpcd_diu_init(void); 27 28 29 /* called before any console output */ 30 int board_early_init_f(void) 31 { 32 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 33 volatile ccsr_gur_t *gur = &immap->im_gur; 34 35 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */ 36 37 return 0; 38 } 39 40 int misc_init_r(void) 41 { 42 u8 tmp_val, version; 43 u8 *pixis_base = (u8 *)PIXIS_BASE; 44 45 /*Do not use 8259PIC*/ 46 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); 47 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80); 48 49 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/ 50 version = in_8(pixis_base + PIXIS_PVER); 51 if(version >= 0x07) { 52 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); 53 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf); 54 } 55 56 /* Using this for DIU init before the driver in linux takes over 57 * Enable the TFP410 Encoder (I2C address 0x38) 58 */ 59 60 tmp_val = 0xBF; 61 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); 62 /* Verify if enabled */ 63 tmp_val = 0; 64 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); 65 debug("DVI Encoder Read: 0x%02x\n", tmp_val); 66 67 tmp_val = 0x10; 68 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); 69 /* Verify if enabled */ 70 tmp_val = 0; 71 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); 72 debug("DVI Encoder Read: 0x%02x\n", tmp_val); 73 74 return 0; 75 } 76 77 int checkboard(void) 78 { 79 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 80 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; 81 u8 *pixis_base = (u8 *)PIXIS_BASE; 82 83 printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, " 84 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 85 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 86 in_8(pixis_base + PIXIS_PVER)); 87 88 /* 89 * The MPC8610 HPCD workbook says that LBMAP=11 is the "normal" boot 90 * bank and LBMAP=00 is the alternate bank. However, the pixis 91 * altbank code can only set bits, not clear them, so we treat 00 as 92 * the normal bank and 11 as the alternate. 93 */ 94 switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) { 95 case 0: 96 puts("vBank: Standard\n"); 97 break; 98 case 0x40: 99 puts("Promjet\n"); 100 break; 101 case 0x80: 102 puts("NAND\n"); 103 break; 104 case 0xC0: 105 puts("vBank: Alternate\n"); 106 break; 107 } 108 109 mcm->abcr |= 0x00010000; /* 0 */ 110 mcm->hpmr3 = 0x80000008; /* 4c */ 111 mcm->hpmr0 = 0; 112 mcm->hpmr1 = 0; 113 mcm->hpmr2 = 0; 114 mcm->hpmr4 = 0; 115 mcm->hpmr5 = 0; 116 117 return 0; 118 } 119 120 121 int initdram(void) 122 { 123 phys_size_t dram_size = 0; 124 125 #if defined(CONFIG_SPD_EEPROM) 126 dram_size = fsl_ddr_sdram(); 127 #else 128 dram_size = fixed_sdram(); 129 #endif 130 131 setup_ddr_bat(dram_size); 132 133 debug(" DDR: "); 134 gd->ram_size = dram_size; 135 136 return 0; 137 } 138 139 140 #if !defined(CONFIG_SPD_EEPROM) 141 /* 142 * Fixed sdram init -- doesn't use serial presence detect. 143 */ 144 145 phys_size_t fixed_sdram(void) 146 { 147 #if !defined(CONFIG_SYS_RAMBOOT) 148 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 149 struct ccsr_ddr __iomem *ddr = &immap->im_ddr1; 150 uint d_init; 151 152 ddr->cs0_bnds = 0x0000001f; 153 ddr->cs0_config = 0x80010202; 154 155 ddr->timing_cfg_3 = 0x00000000; 156 ddr->timing_cfg_0 = 0x00260802; 157 ddr->timing_cfg_1 = 0x3935d322; 158 ddr->timing_cfg_2 = 0x14904cc8; 159 ddr->sdram_mode = 0x00480432; 160 ddr->sdram_mode_2 = 0x00000000; 161 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */ 162 ddr->sdram_data_init = 0xDEADBEEF; 163 ddr->sdram_clk_cntl = 0x03800000; 164 ddr->sdram_cfg_2 = 0x04400010; 165 166 #if defined(CONFIG_DDR_ECC) 167 ddr->err_int_en = 0x0000000d; 168 ddr->err_disable = 0x00000000; 169 ddr->err_sbe = 0x00010000; 170 #endif 171 asm("sync;isync"); 172 173 udelay(500); 174 175 ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/ 176 177 178 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 179 d_init = 1; 180 debug("DDR - 1st controller: memory initializing\n"); 181 /* 182 * Poll until memory is initialized. 183 * 512 Meg at 400 might hit this 200 times or so. 184 */ 185 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) 186 udelay(1000); 187 188 debug("DDR: memory initialized\n\n"); 189 asm("sync; isync"); 190 udelay(500); 191 #endif 192 193 return 512 * 1024 * 1024; 194 #endif 195 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 196 } 197 198 #endif 199 200 #if defined(CONFIG_PCI) 201 /* 202 * Initialize PCI Devices, report devices found. 203 */ 204 205 #ifndef CONFIG_PCI_PNP 206 static struct pci_config_table pci_fsl86xxads_config_table[] = { 207 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 208 PCI_IDSEL_NUMBER, PCI_ANY_ID, 209 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 210 PCI_ENET0_MEMADDR, 211 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} }, 212 {} 213 }; 214 #endif 215 216 217 static struct pci_controller pci1_hose; 218 #endif /* CONFIG_PCI */ 219 220 void pci_init_board(void) 221 { 222 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; 223 volatile ccsr_gur_t *gur = &immap->im_gur; 224 struct fsl_pci_info pci_info; 225 u32 devdisr; 226 int first_free_busno; 227 int pci_agent; 228 229 devdisr = in_be32(&gur->devdisr); 230 231 first_free_busno = fsl_pcie_init_board(0); 232 233 #ifdef CONFIG_PCI1 234 if (!(devdisr & MPC86xx_DEVDISR_PCI1)) { 235 SET_STD_PCI_INFO(pci_info, 1); 236 set_next_law(pci_info.mem_phys, 237 law_size_bits(pci_info.mem_size), pci_info.law); 238 set_next_law(pci_info.io_phys, 239 law_size_bits(pci_info.io_size), pci_info.law); 240 241 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); 242 printf("PCI: connected to PCI slots as %s" \ 243 " (base address %lx)\n", 244 pci_agent ? "Agent" : "Host", 245 pci_info.regs); 246 #ifndef CONFIG_PCI_PNP 247 pci1_hose.config_table = pci_mpc86xxcts_config_table; 248 #endif 249 first_free_busno = fsl_pci_init_port(&pci_info, 250 &pci1_hose, first_free_busno); 251 } else { 252 printf("PCI: disabled\n"); 253 } 254 255 puts("\n"); 256 #else 257 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */ 258 #endif 259 260 fsl_pcie_init_board(first_free_busno); 261 } 262 263 #if defined(CONFIG_OF_BOARD_SETUP) 264 int ft_board_setup(void *blob, bd_t *bd) 265 { 266 ft_cpu_setup(blob, bd); 267 268 FT_FSL_PCI_SETUP; 269 270 return 0; 271 } 272 #endif 273 274 /* 275 * get_board_sys_clk 276 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ 277 */ 278 279 unsigned long 280 get_board_sys_clk(ulong dummy) 281 { 282 u8 i; 283 ulong val = 0; 284 u8 *pixis_base = (u8 *)PIXIS_BASE; 285 286 i = in_8(pixis_base + PIXIS_SPD); 287 i &= 0x07; 288 289 switch (i) { 290 case 0: 291 val = 33333000; 292 break; 293 case 1: 294 val = 39999600; 295 break; 296 case 2: 297 val = 49999500; 298 break; 299 case 3: 300 val = 66666000; 301 break; 302 case 4: 303 val = 83332500; 304 break; 305 case 5: 306 val = 99999000; 307 break; 308 case 6: 309 val = 133332000; 310 break; 311 case 7: 312 val = 166665000; 313 break; 314 } 315 316 return val; 317 } 318 319 int board_eth_init(bd_t *bis) 320 { 321 return pci_eth_init(bis); 322 } 323 324 void board_reset(void) 325 { 326 u8 *pixis_base = (u8 *)PIXIS_BASE; 327 328 out_8(pixis_base + PIXIS_RST, 0); 329 330 while (1) 331 ; 332 } 333