1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/immap_86xx.h> 28 #include <asm/immap_fsl_pci.h> 29 #include <i2c.h> 30 #include <spd.h> 31 #include <asm/io.h> 32 #include <libfdt.h> 33 #include <fdt_support.h> 34 35 #include "../common/pixis.h" 36 37 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 38 extern void ddr_enable_ecc(unsigned int dram_size); 39 #endif 40 41 #if defined(CONFIG_SPD_EEPROM) 42 #include "spd_sdram.h" 43 #endif 44 45 void sdram_init(void); 46 long int fixed_sdram(void); 47 void mpc8610hpcd_diu_init(void); 48 49 50 /* called before any console output */ 51 int board_early_init_f(void) 52 { 53 volatile immap_t *immap = (immap_t *)CFG_IMMR; 54 volatile ccsr_gur_t *gur = &immap->im_gur; 55 56 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */ 57 58 return 0; 59 } 60 61 int misc_init_r(void) 62 { 63 u8 tmp_val, version; 64 65 /*Do not use 8259PIC*/ 66 tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0); 67 out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x80); 68 69 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/ 70 version = in8(PIXIS_BASE + PIXIS_PVER); 71 if(version >= 0x07) { 72 tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0); 73 out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xbf); 74 } 75 76 /* Using this for DIU init before the driver in linux takes over 77 * Enable the TFP410 Encoder (I2C address 0x38) 78 */ 79 80 tmp_val = 0xBF; 81 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); 82 /* Verify if enabled */ 83 tmp_val = 0; 84 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); 85 debug("DVI Encoder Read: 0x%02lx\n",tmp_val); 86 87 tmp_val = 0x10; 88 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); 89 /* Verify if enabled */ 90 tmp_val = 0; 91 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); 92 debug("DVI Encoder Read: 0x%02lx\n",tmp_val); 93 94 #ifdef CONFIG_FSL_DIU_FB 95 mpc8610hpcd_diu_init(); 96 #endif 97 98 return 0; 99 } 100 101 int checkboard(void) 102 { 103 volatile immap_t *immap = (immap_t *)CFG_IMMR; 104 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; 105 106 puts("Board: MPC8610HPCD\n"); 107 108 mcm->abcr |= 0x00010000; /* 0 */ 109 mcm->hpmr3 = 0x80000008; /* 4c */ 110 mcm->hpmr0 = 0; 111 mcm->hpmr1 = 0; 112 mcm->hpmr2 = 0; 113 mcm->hpmr4 = 0; 114 mcm->hpmr5 = 0; 115 116 return 0; 117 } 118 119 120 long int 121 initdram(int board_type) 122 { 123 long dram_size = 0; 124 125 #if defined(CONFIG_SPD_EEPROM) 126 dram_size = spd_sdram(); 127 #else 128 dram_size = fixed_sdram(); 129 #endif 130 131 #if defined(CFG_RAMBOOT) 132 puts(" DDR: "); 133 return dram_size; 134 #endif 135 136 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 137 /* 138 * Initialize and enable DDR ECC. 139 */ 140 ddr_enable_ecc(dram_size); 141 #endif 142 143 puts(" DDR: "); 144 return dram_size; 145 } 146 147 148 #if defined(CFG_DRAM_TEST) 149 int 150 testdram(void) 151 { 152 uint *pstart = (uint *) CFG_MEMTEST_START; 153 uint *pend = (uint *) CFG_MEMTEST_END; 154 uint *p; 155 156 puts("SDRAM test phase 1:\n"); 157 for (p = pstart; p < pend; p++) 158 *p = 0xaaaaaaaa; 159 160 for (p = pstart; p < pend; p++) { 161 if (*p != 0xaaaaaaaa) { 162 printf("SDRAM test fails at: %08x\n", (uint) p); 163 return 1; 164 } 165 } 166 167 puts("SDRAM test phase 2:\n"); 168 for (p = pstart; p < pend; p++) 169 *p = 0x55555555; 170 171 for (p = pstart; p < pend; p++) { 172 if (*p != 0x55555555) { 173 printf("SDRAM test fails at: %08x\n", (uint) p); 174 return 1; 175 } 176 } 177 178 puts("SDRAM test passed.\n"); 179 return 0; 180 } 181 #endif 182 183 184 #if !defined(CONFIG_SPD_EEPROM) 185 /* 186 * Fixed sdram init -- doesn't use serial presence detect. 187 */ 188 189 long int fixed_sdram(void) 190 { 191 #if !defined(CFG_RAMBOOT) 192 volatile immap_t *immap = (immap_t *)CFG_IMMR; 193 volatile ccsr_ddr_t *ddr = &immap->im_ddr1; 194 uint d_init; 195 196 ddr->cs0_bnds = 0x0000001f; 197 ddr->cs0_config = 0x80010202; 198 199 ddr->ext_refrec = 0x00000000; 200 ddr->timing_cfg_0 = 0x00260802; 201 ddr->timing_cfg_1 = 0x3935d322; 202 ddr->timing_cfg_2 = 0x14904cc8; 203 ddr->sdram_mode_1 = 0x00480432; 204 ddr->sdram_mode_2 = 0x00000000; 205 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */ 206 ddr->sdram_data_init = 0xDEADBEEF; 207 ddr->sdram_clk_cntl = 0x03800000; 208 ddr->sdram_cfg_2 = 0x04400010; 209 210 #if defined(CONFIG_DDR_ECC) 211 ddr->err_int_en = 0x0000000d; 212 ddr->err_disable = 0x00000000; 213 ddr->err_sbe = 0x00010000; 214 #endif 215 asm("sync;isync"); 216 217 udelay(500); 218 219 ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/ 220 221 222 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 223 d_init = 1; 224 debug("DDR - 1st controller: memory initializing\n"); 225 /* 226 * Poll until memory is initialized. 227 * 512 Meg at 400 might hit this 200 times or so. 228 */ 229 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) 230 udelay(1000); 231 232 debug("DDR: memory initialized\n\n"); 233 asm("sync; isync"); 234 udelay(500); 235 #endif 236 237 return 512 * 1024 * 1024; 238 #endif 239 return CFG_SDRAM_SIZE * 1024 * 1024; 240 } 241 242 #endif 243 244 #if defined(CONFIG_PCI) 245 /* 246 * Initialize PCI Devices, report devices found. 247 */ 248 249 #ifndef CONFIG_PCI_PNP 250 static struct pci_config_table pci_fsl86xxads_config_table[] = { 251 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 252 PCI_IDSEL_NUMBER, PCI_ANY_ID, 253 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 254 PCI_ENET0_MEMADDR, 255 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} }, 256 {} 257 }; 258 #endif 259 260 261 static struct pci_controller pci1_hose = { 262 #ifndef CONFIG_PCI_PNP 263 config_table:pci_mpc86xxcts_config_table 264 #endif 265 }; 266 #endif /* CONFIG_PCI */ 267 268 #ifdef CONFIG_PCIE1 269 static struct pci_controller pcie1_hose; 270 #endif 271 272 #ifdef CONFIG_PCIE2 273 static struct pci_controller pcie2_hose; 274 #endif 275 276 int first_free_busno = 0; 277 278 void pci_init_board(void) 279 { 280 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; 281 volatile ccsr_gur_t *gur = &immap->im_gur; 282 uint devdisr = gur->devdisr; 283 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 284 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 285 286 printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", 287 devdisr, io_sel, host_agent); 288 289 290 #ifdef CONFIG_PCIE1 291 { 292 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; 293 extern void fsl_pci_init(struct pci_controller *hose); 294 struct pci_controller *hose = &pcie1_hose; 295 int pcie_configured = (io_sel == 1) || (io_sel == 4); 296 int pcie_ep = (host_agent == 0) || (host_agent == 2) || 297 (host_agent == 5); 298 299 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) { 300 printf(" PCIe 1 connected to Uli as %s (base address %x)\n", 301 pcie_ep ? "End Point" : "Root Complex", 302 (uint)pci); 303 if (pci->pme_msg_det) 304 pci->pme_msg_det = 0xffffffff; 305 306 /* inbound */ 307 pci_set_region(hose->regions + 0, 308 CFG_PCI_MEMORY_BUS, 309 CFG_PCI_MEMORY_PHYS, 310 CFG_PCI_MEMORY_SIZE, 311 PCI_REGION_MEM | PCI_REGION_MEMORY); 312 313 /* outbound memory */ 314 pci_set_region(hose->regions + 1, 315 CFG_PCIE1_MEM_BASE, 316 CFG_PCIE1_MEM_PHYS, 317 CFG_PCIE1_MEM_SIZE, 318 PCI_REGION_MEM); 319 320 /* outbound io */ 321 pci_set_region(hose->regions + 2, 322 CFG_PCIE1_IO_BASE, 323 CFG_PCIE1_IO_PHYS, 324 CFG_PCIE1_IO_SIZE, 325 PCI_REGION_IO); 326 327 hose->region_count = 3; 328 329 hose->first_busno = first_free_busno; 330 pci_setup_indirect(hose, (int)&pci->cfg_addr, 331 (int)&pci->cfg_data); 332 333 fsl_pci_init(hose); 334 335 first_free_busno = hose->last_busno + 1; 336 printf(" PCI-Express 1 on bus %02x - %02x\n", 337 hose->first_busno, hose->last_busno); 338 339 } else 340 puts(" PCI-Express 1: Disabled\n"); 341 } 342 #else 343 puts("PCI-Express 1: Disabled\n"); 344 #endif /* CONFIG_PCIE1 */ 345 346 347 #ifdef CONFIG_PCIE2 348 { 349 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR; 350 extern void fsl_pci_init(struct pci_controller *hose); 351 struct pci_controller *hose = &pcie2_hose; 352 353 int pcie_configured = (io_sel == 0) || (io_sel == 4); 354 int pcie_ep = (host_agent == 0) || (host_agent == 1) || 355 (host_agent == 4); 356 357 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) { 358 printf(" PCI-Express 2 connected to slot as %s" \ 359 " (base address %x)\n", 360 pcie_ep ? "End Point" : "Root Complex", 361 (uint)pci); 362 if (pci->pme_msg_det) 363 pci->pme_msg_det = 0xffffffff; 364 365 /* inbound */ 366 pci_set_region(hose->regions + 0, 367 CFG_PCI_MEMORY_BUS, 368 CFG_PCI_MEMORY_PHYS, 369 CFG_PCI_MEMORY_SIZE, 370 PCI_REGION_MEM | PCI_REGION_MEMORY); 371 372 /* outbound memory */ 373 pci_set_region(hose->regions + 1, 374 CFG_PCIE2_MEM_BASE, 375 CFG_PCIE2_MEM_PHYS, 376 CFG_PCIE2_MEM_SIZE, 377 PCI_REGION_MEM); 378 379 /* outbound io */ 380 pci_set_region(hose->regions + 2, 381 CFG_PCIE2_IO_BASE, 382 CFG_PCIE2_IO_PHYS, 383 CFG_PCIE2_IO_SIZE, 384 PCI_REGION_IO); 385 386 hose->region_count = 3; 387 388 hose->first_busno = first_free_busno; 389 pci_setup_indirect(hose, (int)&pci->cfg_addr, 390 (int)&pci->cfg_data); 391 392 fsl_pci_init(hose); 393 394 first_free_busno = hose->last_busno + 1; 395 printf(" PCI-Express 2 on bus %02x - %02x\n", 396 hose->first_busno, hose->last_busno); 397 } else 398 puts(" PCI-Express 2: Disabled\n"); 399 } 400 #else 401 puts("PCI-Express 2: Disabled\n"); 402 #endif /* CONFIG_PCIE2 */ 403 404 405 #ifdef CONFIG_PCI1 406 { 407 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; 408 extern void fsl_pci_init(struct pci_controller *hose); 409 struct pci_controller *hose = &pci1_hose; 410 int pci_agent = (host_agent >= 4) && (host_agent <= 6); 411 412 if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) { 413 printf(" PCI connected to PCI slots as %s" \ 414 " (base address %x)\n", 415 pci_agent ? "Agent" : "Host", 416 (uint)pci); 417 418 /* inbound */ 419 pci_set_region(hose->regions + 0, 420 CFG_PCI_MEMORY_BUS, 421 CFG_PCI_MEMORY_PHYS, 422 CFG_PCI_MEMORY_SIZE, 423 PCI_REGION_MEM | PCI_REGION_MEMORY); 424 425 /* outbound memory */ 426 pci_set_region(hose->regions + 1, 427 CFG_PCI1_MEM_BASE, 428 CFG_PCI1_MEM_PHYS, 429 CFG_PCI1_MEM_SIZE, 430 PCI_REGION_MEM); 431 432 /* outbound io */ 433 pci_set_region(hose->regions + 2, 434 CFG_PCI1_IO_BASE, 435 CFG_PCI1_IO_PHYS, 436 CFG_PCI1_IO_SIZE, 437 PCI_REGION_IO); 438 439 hose->region_count = 3; 440 441 hose->first_busno = first_free_busno; 442 pci_setup_indirect(hose, (int) &pci->cfg_addr, 443 (int) &pci->cfg_data); 444 445 fsl_pci_init(hose); 446 447 first_free_busno = hose->last_busno + 1; 448 printf(" PCI on bus %02x - %02x\n", 449 hose->first_busno, hose->last_busno); 450 451 452 } else 453 puts(" PCI: Disabled\n"); 454 } 455 #endif /* CONFIG_PCI1 */ 456 } 457 458 #if defined(CONFIG_OF_BOARD_SETUP) 459 void 460 ft_board_setup(void *blob, bd_t *bd) 461 { 462 int node, tmp[2]; 463 const char *path; 464 465 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 466 "timebase-frequency", bd->bi_busfreq / 4, 1); 467 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 468 "bus-frequency", bd->bi_busfreq, 1); 469 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 470 "clock-frequency", bd->bi_intfreq, 1); 471 do_fixup_by_prop_u32(blob, "device_type", "soc", 4, 472 "bus-frequency", bd->bi_busfreq, 1); 473 474 do_fixup_by_compat_u32(blob, "ns16550", 475 "clock-frequency", bd->bi_busfreq, 1); 476 477 fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize); 478 479 480 node = fdt_path_offset(blob, "/aliases"); 481 tmp[0] = 0; 482 if (node >= 0) { 483 484 #ifdef CONFIG_PCI1 485 path = fdt_getprop(blob, node, "pci0", NULL); 486 if (path) { 487 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; 488 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 489 } 490 491 #endif 492 #ifdef CONFIG_PCIE1 493 path = fdt_getprop(blob, node, "pci1", NULL); 494 if (path) { 495 tmp[1] = pcie1_hose.last_busno 496 - pcie1_hose.first_busno; 497 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 498 } 499 #endif 500 #ifdef CONFIG_PCIE2 501 path = fdt_getprop(blob, node, "pci2", NULL); 502 if (path) { 503 tmp[1] = pcie2_hose.last_busno 504 - pcie2_hose.first_busno; 505 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 506 } 507 #endif 508 } 509 } 510 #endif 511 512 /* 513 * get_board_sys_clk 514 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ 515 */ 516 517 unsigned long 518 get_board_sys_clk(ulong dummy) 519 { 520 u8 i; 521 ulong val = 0; 522 ulong a; 523 524 a = PIXIS_BASE + PIXIS_SPD; 525 i = in8(a); 526 i &= 0x07; 527 528 switch (i) { 529 case 0: 530 val = 33333000; 531 break; 532 case 1: 533 val = 39999600; 534 break; 535 case 2: 536 val = 49999500; 537 break; 538 case 3: 539 val = 66666000; 540 break; 541 case 4: 542 val = 83332500; 543 break; 544 case 5: 545 val = 99999000; 546 break; 547 case 6: 548 val = 133332000; 549 break; 550 case 7: 551 val = 166665000; 552 break; 553 } 554 555 return val; 556 } 557