1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/immap_86xx.h> 28 #include <asm/fsl_pci.h> 29 #include <asm/fsl_ddr_sdram.h> 30 #include <i2c.h> 31 #include <asm/io.h> 32 #include <libfdt.h> 33 #include <fdt_support.h> 34 #include <spd_sdram.h> 35 #include <netdev.h> 36 37 #include "../common/pixis.h" 38 39 void sdram_init(void); 40 phys_size_t fixed_sdram(void); 41 void mpc8610hpcd_diu_init(void); 42 43 44 /* called before any console output */ 45 int board_early_init_f(void) 46 { 47 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 48 volatile ccsr_gur_t *gur = &immap->im_gur; 49 50 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */ 51 52 return 0; 53 } 54 55 int misc_init_r(void) 56 { 57 u8 tmp_val, version; 58 59 /*Do not use 8259PIC*/ 60 tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0); 61 out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x80); 62 63 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/ 64 version = in8(PIXIS_BASE + PIXIS_PVER); 65 if(version >= 0x07) { 66 tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0); 67 out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xbf); 68 } 69 70 /* Using this for DIU init before the driver in linux takes over 71 * Enable the TFP410 Encoder (I2C address 0x38) 72 */ 73 74 tmp_val = 0xBF; 75 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); 76 /* Verify if enabled */ 77 tmp_val = 0; 78 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); 79 debug("DVI Encoder Read: 0x%02lx\n",tmp_val); 80 81 tmp_val = 0x10; 82 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); 83 /* Verify if enabled */ 84 tmp_val = 0; 85 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); 86 debug("DVI Encoder Read: 0x%02lx\n",tmp_val); 87 88 #ifdef CONFIG_FSL_DIU_FB 89 mpc8610hpcd_diu_init(); 90 #endif 91 92 return 0; 93 } 94 95 int checkboard(void) 96 { 97 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 98 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; 99 100 printf ("Board: MPC8610HPCD, System ID: 0x%02x, " 101 "System Version: 0x%02x, FPGA Version: 0x%02x\n", 102 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), 103 in8(PIXIS_BASE + PIXIS_PVER)); 104 105 mcm->abcr |= 0x00010000; /* 0 */ 106 mcm->hpmr3 = 0x80000008; /* 4c */ 107 mcm->hpmr0 = 0; 108 mcm->hpmr1 = 0; 109 mcm->hpmr2 = 0; 110 mcm->hpmr4 = 0; 111 mcm->hpmr5 = 0; 112 113 return 0; 114 } 115 116 117 phys_size_t 118 initdram(int board_type) 119 { 120 phys_size_t dram_size = 0; 121 122 #if defined(CONFIG_SPD_EEPROM) 123 dram_size = fsl_ddr_sdram(); 124 #else 125 dram_size = fixed_sdram(); 126 #endif 127 128 #if defined(CONFIG_SYS_RAMBOOT) 129 puts(" DDR: "); 130 return dram_size; 131 #endif 132 133 puts(" DDR: "); 134 return dram_size; 135 } 136 137 138 #if !defined(CONFIG_SPD_EEPROM) 139 /* 140 * Fixed sdram init -- doesn't use serial presence detect. 141 */ 142 143 phys_size_t fixed_sdram(void) 144 { 145 #if !defined(CONFIG_SYS_RAMBOOT) 146 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 147 volatile ccsr_ddr_t *ddr = &immap->im_ddr1; 148 uint d_init; 149 150 ddr->cs0_bnds = 0x0000001f; 151 ddr->cs0_config = 0x80010202; 152 153 ddr->timing_cfg_3 = 0x00000000; 154 ddr->timing_cfg_0 = 0x00260802; 155 ddr->timing_cfg_1 = 0x3935d322; 156 ddr->timing_cfg_2 = 0x14904cc8; 157 ddr->sdram_mode_1 = 0x00480432; 158 ddr->sdram_mode_2 = 0x00000000; 159 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */ 160 ddr->sdram_data_init = 0xDEADBEEF; 161 ddr->sdram_clk_cntl = 0x03800000; 162 ddr->sdram_cfg_2 = 0x04400010; 163 164 #if defined(CONFIG_DDR_ECC) 165 ddr->err_int_en = 0x0000000d; 166 ddr->err_disable = 0x00000000; 167 ddr->err_sbe = 0x00010000; 168 #endif 169 asm("sync;isync"); 170 171 udelay(500); 172 173 ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/ 174 175 176 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 177 d_init = 1; 178 debug("DDR - 1st controller: memory initializing\n"); 179 /* 180 * Poll until memory is initialized. 181 * 512 Meg at 400 might hit this 200 times or so. 182 */ 183 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) 184 udelay(1000); 185 186 debug("DDR: memory initialized\n\n"); 187 asm("sync; isync"); 188 udelay(500); 189 #endif 190 191 return 512 * 1024 * 1024; 192 #endif 193 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 194 } 195 196 #endif 197 198 #if defined(CONFIG_PCI) 199 /* 200 * Initialize PCI Devices, report devices found. 201 */ 202 203 #ifndef CONFIG_PCI_PNP 204 static struct pci_config_table pci_fsl86xxads_config_table[] = { 205 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 206 PCI_IDSEL_NUMBER, PCI_ANY_ID, 207 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 208 PCI_ENET0_MEMADDR, 209 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} }, 210 {} 211 }; 212 #endif 213 214 215 static struct pci_controller pci1_hose = { 216 #ifndef CONFIG_PCI_PNP 217 config_table:pci_mpc86xxcts_config_table 218 #endif 219 }; 220 #endif /* CONFIG_PCI */ 221 222 #ifdef CONFIG_PCIE1 223 static struct pci_controller pcie1_hose; 224 #endif 225 226 #ifdef CONFIG_PCIE2 227 static struct pci_controller pcie2_hose; 228 #endif 229 230 int first_free_busno = 0; 231 232 void pci_init_board(void) 233 { 234 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; 235 volatile ccsr_gur_t *gur = &immap->im_gur; 236 uint devdisr = gur->devdisr; 237 uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL) 238 >> MPC8610_PORDEVSR_IO_SEL_SHIFT; 239 uint host_agent = (gur->porbmsr & MPC8610_PORBMSR_HA) 240 >> MPC8610_PORBMSR_HA_SHIFT; 241 242 printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", 243 devdisr, io_sel, host_agent); 244 245 #ifdef CONFIG_PCIE1 246 { 247 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 248 struct pci_controller *hose = &pcie1_hose; 249 int pcie_configured = (io_sel == 1) || (io_sel == 4); 250 int pcie_ep = (host_agent == 0) || (host_agent == 2) || 251 (host_agent == 5); 252 struct pci_region *r = hose->regions; 253 254 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) { 255 printf(" PCIe 1 connected to Uli as %s (base address %x)\n", 256 pcie_ep ? "End Point" : "Root Complex", 257 (uint)pci); 258 if (pci->pme_msg_det) 259 pci->pme_msg_det = 0xffffffff; 260 261 /* inbound */ 262 r += fsl_pci_setup_inbound_windows(r); 263 264 /* outbound memory */ 265 pci_set_region(r++, 266 CONFIG_SYS_PCIE1_MEM_BUS, 267 CONFIG_SYS_PCIE1_MEM_PHYS, 268 CONFIG_SYS_PCIE1_MEM_SIZE, 269 PCI_REGION_MEM); 270 271 /* outbound io */ 272 pci_set_region(r++, 273 CONFIG_SYS_PCIE1_IO_BUS, 274 CONFIG_SYS_PCIE1_IO_PHYS, 275 CONFIG_SYS_PCIE1_IO_SIZE, 276 PCI_REGION_IO); 277 278 hose->region_count = r - hose->regions; 279 280 hose->first_busno = first_free_busno; 281 pci_setup_indirect(hose, (int)&pci->cfg_addr, 282 (int)&pci->cfg_data); 283 284 fsl_pci_init(hose); 285 286 first_free_busno = hose->last_busno + 1; 287 printf(" PCI-Express 1 on bus %02x - %02x\n", 288 hose->first_busno, hose->last_busno); 289 290 } else 291 puts(" PCI-Express 1: Disabled\n"); 292 } 293 #else 294 puts("PCI-Express 1: Disabled\n"); 295 #endif /* CONFIG_PCIE1 */ 296 297 298 #ifdef CONFIG_PCIE2 299 { 300 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; 301 struct pci_controller *hose = &pcie2_hose; 302 struct pci_region *r = hose->regions; 303 304 int pcie_configured = (io_sel == 0) || (io_sel == 4); 305 int pcie_ep = (host_agent == 0) || (host_agent == 1) || 306 (host_agent == 4); 307 308 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) { 309 printf(" PCI-Express 2 connected to slot as %s" \ 310 " (base address %x)\n", 311 pcie_ep ? "End Point" : "Root Complex", 312 (uint)pci); 313 if (pci->pme_msg_det) 314 pci->pme_msg_det = 0xffffffff; 315 316 /* inbound */ 317 r += fsl_pci_setup_inbound_windows(r); 318 319 /* outbound memory */ 320 pci_set_region(r++, 321 CONFIG_SYS_PCIE2_MEM_BUS, 322 CONFIG_SYS_PCIE2_MEM_PHYS, 323 CONFIG_SYS_PCIE2_MEM_SIZE, 324 PCI_REGION_MEM); 325 326 /* outbound io */ 327 pci_set_region(r++, 328 CONFIG_SYS_PCIE2_IO_BUS, 329 CONFIG_SYS_PCIE2_IO_PHYS, 330 CONFIG_SYS_PCIE2_IO_SIZE, 331 PCI_REGION_IO); 332 333 hose->region_count = r - hose->regions; 334 335 hose->first_busno = first_free_busno; 336 pci_setup_indirect(hose, (int)&pci->cfg_addr, 337 (int)&pci->cfg_data); 338 339 fsl_pci_init(hose); 340 341 first_free_busno = hose->last_busno + 1; 342 printf(" PCI-Express 2 on bus %02x - %02x\n", 343 hose->first_busno, hose->last_busno); 344 } else 345 puts(" PCI-Express 2: Disabled\n"); 346 } 347 #else 348 puts("PCI-Express 2: Disabled\n"); 349 #endif /* CONFIG_PCIE2 */ 350 351 352 #ifdef CONFIG_PCI1 353 { 354 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; 355 struct pci_controller *hose = &pci1_hose; 356 int pci_agent = (host_agent >= 4) && (host_agent <= 6); 357 struct pci_region *r = hose->regions; 358 359 if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) { 360 printf(" PCI connected to PCI slots as %s" \ 361 " (base address %x)\n", 362 pci_agent ? "Agent" : "Host", 363 (uint)pci); 364 365 /* inbound */ 366 r += fsl_pci_setup_inbound_windows(r); 367 368 /* outbound memory */ 369 pci_set_region(r++, 370 CONFIG_SYS_PCI1_MEM_BUS, 371 CONFIG_SYS_PCI1_MEM_PHYS, 372 CONFIG_SYS_PCI1_MEM_SIZE, 373 PCI_REGION_MEM); 374 375 /* outbound io */ 376 pci_set_region(r++, 377 CONFIG_SYS_PCI1_IO_BUS, 378 CONFIG_SYS_PCI1_IO_PHYS, 379 CONFIG_SYS_PCI1_IO_SIZE, 380 PCI_REGION_IO); 381 382 hose->region_count = r - hose->regions; 383 384 hose->first_busno = first_free_busno; 385 pci_setup_indirect(hose, (int) &pci->cfg_addr, 386 (int) &pci->cfg_data); 387 388 fsl_pci_init(hose); 389 390 first_free_busno = hose->last_busno + 1; 391 printf(" PCI on bus %02x - %02x\n", 392 hose->first_busno, hose->last_busno); 393 394 395 } else 396 puts(" PCI: Disabled\n"); 397 } 398 #endif /* CONFIG_PCI1 */ 399 } 400 401 #if defined(CONFIG_OF_BOARD_SETUP) 402 void 403 ft_board_setup(void *blob, bd_t *bd) 404 { 405 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 406 "timebase-frequency", bd->bi_busfreq / 4, 1); 407 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 408 "bus-frequency", bd->bi_busfreq, 1); 409 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 410 "clock-frequency", bd->bi_intfreq, 1); 411 do_fixup_by_prop_u32(blob, "device_type", "soc", 4, 412 "bus-frequency", bd->bi_busfreq, 1); 413 414 do_fixup_by_compat_u32(blob, "ns16550", 415 "clock-frequency", bd->bi_busfreq, 1); 416 417 fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize); 418 419 #ifdef CONFIG_PCI1 420 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 421 #endif 422 #ifdef CONFIG_PCIE1 423 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); 424 #endif 425 #ifdef CONFIG_PCIE2 426 ft_fsl_pci_setup(blob, "pci2", &pcie2_hose); 427 #endif 428 } 429 #endif 430 431 /* 432 * get_board_sys_clk 433 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ 434 */ 435 436 unsigned long 437 get_board_sys_clk(ulong dummy) 438 { 439 u8 i; 440 ulong val = 0; 441 ulong a; 442 443 a = PIXIS_BASE + PIXIS_SPD; 444 i = in8(a); 445 i &= 0x07; 446 447 switch (i) { 448 case 0: 449 val = 33333000; 450 break; 451 case 1: 452 val = 39999600; 453 break; 454 case 2: 455 val = 49999500; 456 break; 457 case 3: 458 val = 66666000; 459 break; 460 case 4: 461 val = 83332500; 462 break; 463 case 5: 464 val = 99999000; 465 break; 466 case 6: 467 val = 133332000; 468 break; 469 case 7: 470 val = 166665000; 471 break; 472 } 473 474 return val; 475 } 476 477 int board_eth_init(bd_t *bis) 478 { 479 return pci_eth_init(bis); 480 } 481 482 void board_reset(void) 483 { 484 out8(PIXIS_BASE + PIXIS_RST, 0); 485 486 while (1) 487 ; 488 } 489