1 /* 2 * Copyright 2007,2009-2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/immap_86xx.h> 28 #include <asm/fsl_pci.h> 29 #include <asm/fsl_ddr_sdram.h> 30 #include <i2c.h> 31 #include <asm/io.h> 32 #include <libfdt.h> 33 #include <fdt_support.h> 34 #include <spd_sdram.h> 35 #include <netdev.h> 36 37 void sdram_init(void); 38 phys_size_t fixed_sdram(void); 39 void mpc8610hpcd_diu_init(void); 40 41 42 /* called before any console output */ 43 int board_early_init_f(void) 44 { 45 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 46 volatile ccsr_gur_t *gur = &immap->im_gur; 47 48 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */ 49 50 return 0; 51 } 52 53 int misc_init_r(void) 54 { 55 u8 tmp_val, version; 56 u8 *pixis_base = (u8 *)PIXIS_BASE; 57 58 /*Do not use 8259PIC*/ 59 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); 60 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80); 61 62 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/ 63 version = in_8(pixis_base + PIXIS_PVER); 64 if(version >= 0x07) { 65 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); 66 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf); 67 } 68 69 /* Using this for DIU init before the driver in linux takes over 70 * Enable the TFP410 Encoder (I2C address 0x38) 71 */ 72 73 tmp_val = 0xBF; 74 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); 75 /* Verify if enabled */ 76 tmp_val = 0; 77 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); 78 debug("DVI Encoder Read: 0x%02lx\n",tmp_val); 79 80 tmp_val = 0x10; 81 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); 82 /* Verify if enabled */ 83 tmp_val = 0; 84 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); 85 debug("DVI Encoder Read: 0x%02lx\n",tmp_val); 86 87 #ifdef CONFIG_FSL_DIU_FB 88 mpc8610hpcd_diu_init(); 89 #endif 90 91 return 0; 92 } 93 94 int checkboard(void) 95 { 96 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 97 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; 98 u8 *pixis_base = (u8 *)PIXIS_BASE; 99 100 printf ("Board: MPC8610HPCD, System ID: 0x%02x, " 101 "System Version: 0x%02x, FPGA Version: 0x%02x\n", 102 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 103 in_8(pixis_base + PIXIS_PVER)); 104 105 mcm->abcr |= 0x00010000; /* 0 */ 106 mcm->hpmr3 = 0x80000008; /* 4c */ 107 mcm->hpmr0 = 0; 108 mcm->hpmr1 = 0; 109 mcm->hpmr2 = 0; 110 mcm->hpmr4 = 0; 111 mcm->hpmr5 = 0; 112 113 return 0; 114 } 115 116 117 phys_size_t 118 initdram(int board_type) 119 { 120 phys_size_t dram_size = 0; 121 122 #if defined(CONFIG_SPD_EEPROM) 123 dram_size = fsl_ddr_sdram(); 124 #else 125 dram_size = fixed_sdram(); 126 #endif 127 128 setup_ddr_bat(dram_size); 129 130 puts(" DDR: "); 131 return dram_size; 132 } 133 134 135 #if !defined(CONFIG_SPD_EEPROM) 136 /* 137 * Fixed sdram init -- doesn't use serial presence detect. 138 */ 139 140 phys_size_t fixed_sdram(void) 141 { 142 #if !defined(CONFIG_SYS_RAMBOOT) 143 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 144 volatile ccsr_ddr_t *ddr = &immap->im_ddr1; 145 uint d_init; 146 147 ddr->cs0_bnds = 0x0000001f; 148 ddr->cs0_config = 0x80010202; 149 150 ddr->timing_cfg_3 = 0x00000000; 151 ddr->timing_cfg_0 = 0x00260802; 152 ddr->timing_cfg_1 = 0x3935d322; 153 ddr->timing_cfg_2 = 0x14904cc8; 154 ddr->sdram_mode = 0x00480432; 155 ddr->sdram_mode_2 = 0x00000000; 156 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */ 157 ddr->sdram_data_init = 0xDEADBEEF; 158 ddr->sdram_clk_cntl = 0x03800000; 159 ddr->sdram_cfg_2 = 0x04400010; 160 161 #if defined(CONFIG_DDR_ECC) 162 ddr->err_int_en = 0x0000000d; 163 ddr->err_disable = 0x00000000; 164 ddr->err_sbe = 0x00010000; 165 #endif 166 asm("sync;isync"); 167 168 udelay(500); 169 170 ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/ 171 172 173 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 174 d_init = 1; 175 debug("DDR - 1st controller: memory initializing\n"); 176 /* 177 * Poll until memory is initialized. 178 * 512 Meg at 400 might hit this 200 times or so. 179 */ 180 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) 181 udelay(1000); 182 183 debug("DDR: memory initialized\n\n"); 184 asm("sync; isync"); 185 udelay(500); 186 #endif 187 188 return 512 * 1024 * 1024; 189 #endif 190 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 191 } 192 193 #endif 194 195 #if defined(CONFIG_PCI) 196 /* 197 * Initialize PCI Devices, report devices found. 198 */ 199 200 #ifndef CONFIG_PCI_PNP 201 static struct pci_config_table pci_fsl86xxads_config_table[] = { 202 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 203 PCI_IDSEL_NUMBER, PCI_ANY_ID, 204 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 205 PCI_ENET0_MEMADDR, 206 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} }, 207 {} 208 }; 209 #endif 210 211 212 static struct pci_controller pci1_hose = { 213 #ifndef CONFIG_PCI_PNP 214 config_table:pci_mpc86xxcts_config_table 215 #endif 216 }; 217 #endif /* CONFIG_PCI */ 218 219 #ifdef CONFIG_PCIE1 220 static struct pci_controller pcie1_hose; 221 #endif 222 223 #ifdef CONFIG_PCIE2 224 static struct pci_controller pcie2_hose; 225 #endif 226 227 void pci_init_board(void) 228 { 229 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; 230 volatile ccsr_gur_t *gur = &immap->im_gur; 231 struct fsl_pci_info pci_info[3]; 232 u32 devdisr, pordevsr, io_sel; 233 int first_free_busno = 0; 234 int num = 0; 235 236 int pci_agent, pcie_ep, pcie_configured; 237 238 devdisr = in_be32(&gur->devdisr); 239 pordevsr = in_be32(&gur->pordevsr); 240 io_sel = (pordevsr & MPC8610_PORDEVSR_IO_SEL) 241 >> MPC8610_PORDEVSR_IO_SEL_SHIFT; 242 243 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 244 245 #ifdef CONFIG_PCIE1 246 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 247 248 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){ 249 SET_STD_PCIE_INFO(pci_info[num], 1); 250 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 251 printf (" PCIE1 connected to ULI as %s (base addr %lx)\n", 252 pcie_ep ? "Endpoint" : "Root Complex", 253 pci_info[num].regs); 254 255 first_free_busno = fsl_pci_init_port(&pci_info[num++], 256 &pcie1_hose, first_free_busno); 257 } else { 258 printf (" PCIE1: disabled\n"); 259 } 260 261 puts("\n"); 262 #else 263 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE1); /* disable */ 264 #endif 265 266 #ifdef CONFIG_PCIE2 267 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); 268 269 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){ 270 SET_STD_PCIE_INFO(pci_info[num], 2); 271 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); 272 printf (" PCIE2 connected to Slot as %s (base addr %lx)\n", 273 pcie_ep ? "Endpoint" : "Root Complex", 274 pci_info[num].regs); 275 first_free_busno = fsl_pci_init_port(&pci_info[num++], 276 &pcie2_hose, first_free_busno); 277 } else { 278 printf (" PCIE2: disabled\n"); 279 } 280 281 puts("\n"); 282 #else 283 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE2); /* disable */ 284 #endif 285 286 #ifdef CONFIG_PCI1 287 if (!(devdisr & MPC86xx_DEVDISR_PCI1)) { 288 SET_STD_PCI_INFO(pci_info[num], 1); 289 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); 290 printf(" PCI connected to PCI slots as %s" \ 291 " (base address %lx)\n", 292 pci_agent ? "Agent" : "Host", 293 pci_info[num].regs); 294 first_free_busno = fsl_pci_init_port(&pci_info[num++], 295 &pci1_hose, first_free_busno); 296 } else { 297 printf (" PCI: disabled\n"); 298 } 299 300 puts("\n"); 301 #else 302 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */ 303 #endif 304 } 305 306 #if defined(CONFIG_OF_BOARD_SETUP) 307 void 308 ft_board_setup(void *blob, bd_t *bd) 309 { 310 ft_cpu_setup(blob, bd); 311 312 FT_FSL_PCI_SETUP; 313 } 314 #endif 315 316 /* 317 * get_board_sys_clk 318 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ 319 */ 320 321 unsigned long 322 get_board_sys_clk(ulong dummy) 323 { 324 u8 i; 325 ulong val = 0; 326 u8 *pixis_base = (u8 *)PIXIS_BASE; 327 328 i = in_8(pixis_base + PIXIS_SPD); 329 i &= 0x07; 330 331 switch (i) { 332 case 0: 333 val = 33333000; 334 break; 335 case 1: 336 val = 39999600; 337 break; 338 case 2: 339 val = 49999500; 340 break; 341 case 3: 342 val = 66666000; 343 break; 344 case 4: 345 val = 83332500; 346 break; 347 case 5: 348 val = 99999000; 349 break; 350 case 6: 351 val = 133332000; 352 break; 353 case 7: 354 val = 166665000; 355 break; 356 } 357 358 return val; 359 } 360 361 int board_eth_init(bd_t *bis) 362 { 363 return pci_eth_init(bis); 364 } 365 366 void board_reset(void) 367 { 368 u8 *pixis_base = (u8 *)PIXIS_BASE; 369 370 out_8(pixis_base + PIXIS_RST, 0); 371 372 while (1) 373 ; 374 } 375