1 /*
2  * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <command.h>
9 #include <pci.h>
10 #include <asm/processor.h>
11 #include <asm/immap_86xx.h>
12 #include <asm/fsl_pci.h>
13 #include <fsl_ddr_sdram.h>
14 #include <asm/fsl_serdes.h>
15 #include <i2c.h>
16 #include <asm/io.h>
17 #include <libfdt.h>
18 #include <fdt_support.h>
19 #include <spd_sdram.h>
20 #include <netdev.h>
21 
22 void sdram_init(void);
23 phys_size_t fixed_sdram(void);
24 int mpc8610hpcd_diu_init(void);
25 
26 
27 /* called before any console output */
28 int board_early_init_f(void)
29 {
30 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
31 	volatile ccsr_gur_t *gur = &immap->im_gur;
32 
33 	gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
34 
35 	return 0;
36 }
37 
38 int misc_init_r(void)
39 {
40 	u8 tmp_val, version;
41 	u8 *pixis_base = (u8 *)PIXIS_BASE;
42 
43 	/*Do not use 8259PIC*/
44 	tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
45 	out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
46 
47 	/*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
48 	version = in_8(pixis_base + PIXIS_PVER);
49 	if(version >= 0x07) {
50 		tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
51 		out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
52 	}
53 
54 	/* Using this for DIU init before the driver in linux takes over
55 	 *  Enable the TFP410 Encoder (I2C address 0x38)
56 	 */
57 
58 	tmp_val = 0xBF;
59 	i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
60 	/* Verify if enabled */
61 	tmp_val = 0;
62 	i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
63 	debug("DVI Encoder Read: 0x%02x\n", tmp_val);
64 
65 	tmp_val = 0x10;
66 	i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
67 	/* Verify if enabled */
68 	tmp_val = 0;
69 	i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
70 	debug("DVI Encoder Read: 0x%02x\n", tmp_val);
71 
72 	return 0;
73 }
74 
75 int checkboard(void)
76 {
77 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
78 	volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
79 	u8 *pixis_base = (u8 *)PIXIS_BASE;
80 
81 	printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, "
82 		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
83 		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
84 		in_8(pixis_base + PIXIS_PVER));
85 
86 	/*
87 	 * The MPC8610 HPCD workbook says that LBMAP=11 is the "normal" boot
88 	 * bank and LBMAP=00 is the alternate bank.  However, the pixis
89 	 * altbank code can only set bits, not clear them, so we treat 00 as
90 	 * the normal bank and 11 as the alternate.
91 	 */
92 	switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) {
93 	case 0:
94 		puts("vBank: Standard\n");
95 		break;
96 	case 0x40:
97 		puts("Promjet\n");
98 		break;
99 	case 0x80:
100 		puts("NAND\n");
101 		break;
102 	case 0xC0:
103 		puts("vBank: Alternate\n");
104 		break;
105 	}
106 
107 	mcm->abcr |= 0x00010000; /* 0 */
108 	mcm->hpmr3 = 0x80000008; /* 4c */
109 	mcm->hpmr0 = 0;
110 	mcm->hpmr1 = 0;
111 	mcm->hpmr2 = 0;
112 	mcm->hpmr4 = 0;
113 	mcm->hpmr5 = 0;
114 
115 	return 0;
116 }
117 
118 
119 phys_size_t
120 initdram(int board_type)
121 {
122 	phys_size_t dram_size = 0;
123 
124 #if defined(CONFIG_SPD_EEPROM)
125 	dram_size = fsl_ddr_sdram();
126 #else
127 	dram_size = fixed_sdram();
128 #endif
129 
130 	setup_ddr_bat(dram_size);
131 
132 	debug(" DDR: ");
133 	return dram_size;
134 }
135 
136 
137 #if !defined(CONFIG_SPD_EEPROM)
138 /*
139  * Fixed sdram init -- doesn't use serial presence detect.
140  */
141 
142 phys_size_t fixed_sdram(void)
143 {
144 #if !defined(CONFIG_SYS_RAMBOOT)
145 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
146 	struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
147 	uint d_init;
148 
149 	ddr->cs0_bnds = 0x0000001f;
150 	ddr->cs0_config = 0x80010202;
151 
152 	ddr->timing_cfg_3 = 0x00000000;
153 	ddr->timing_cfg_0 = 0x00260802;
154 	ddr->timing_cfg_1 = 0x3935d322;
155 	ddr->timing_cfg_2 = 0x14904cc8;
156 	ddr->sdram_mode = 0x00480432;
157 	ddr->sdram_mode_2 = 0x00000000;
158 	ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
159 	ddr->sdram_data_init = 0xDEADBEEF;
160 	ddr->sdram_clk_cntl = 0x03800000;
161 	ddr->sdram_cfg_2 = 0x04400010;
162 
163 #if defined(CONFIG_DDR_ECC)
164 	ddr->err_int_en = 0x0000000d;
165 	ddr->err_disable = 0x00000000;
166 	ddr->err_sbe = 0x00010000;
167 #endif
168 	asm("sync;isync");
169 
170 	udelay(500);
171 
172 	ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
173 
174 
175 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
176 	d_init = 1;
177 	debug("DDR - 1st controller: memory initializing\n");
178 	/*
179 	 * Poll until memory is initialized.
180 	 * 512 Meg at 400 might hit this 200 times or so.
181 	 */
182 	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
183 		udelay(1000);
184 
185 	debug("DDR: memory initialized\n\n");
186 	asm("sync; isync");
187 	udelay(500);
188 #endif
189 
190 	return 512 * 1024 * 1024;
191 #endif
192 	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
193 }
194 
195 #endif
196 
197 #if defined(CONFIG_PCI)
198 /*
199  * Initialize PCI Devices, report devices found.
200  */
201 
202 #ifndef CONFIG_PCI_PNP
203 static struct pci_config_table pci_fsl86xxads_config_table[] = {
204 	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
205 	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
206 	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
207 				 PCI_ENET0_MEMADDR,
208 				 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
209 	{}
210 };
211 #endif
212 
213 
214 static struct pci_controller pci1_hose;
215 #endif /* CONFIG_PCI */
216 
217 void pci_init_board(void)
218 {
219 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
220 	volatile ccsr_gur_t *gur = &immap->im_gur;
221 	struct fsl_pci_info pci_info;
222 	u32 devdisr;
223 	int first_free_busno;
224 	int pci_agent;
225 
226 	devdisr = in_be32(&gur->devdisr);
227 
228 	first_free_busno = fsl_pcie_init_board(0);
229 
230 #ifdef CONFIG_PCI1
231 	if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
232 		SET_STD_PCI_INFO(pci_info, 1);
233 		set_next_law(pci_info.mem_phys,
234 			law_size_bits(pci_info.mem_size), pci_info.law);
235 		set_next_law(pci_info.io_phys,
236 			law_size_bits(pci_info.io_size), pci_info.law);
237 
238 		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
239 		printf("PCI: connected to PCI slots as %s" \
240 			" (base address %lx)\n",
241 			pci_agent ? "Agent" : "Host",
242 			pci_info.regs);
243 #ifndef CONFIG_PCI_PNP
244 		pci1_hose.config_table = pci_mpc86xxcts_config_table;
245 #endif
246 		first_free_busno = fsl_pci_init_port(&pci_info,
247 					&pci1_hose, first_free_busno);
248 	} else {
249 		printf("PCI: disabled\n");
250 	}
251 
252 	puts("\n");
253 #else
254 	setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
255 #endif
256 
257 	fsl_pcie_init_board(first_free_busno);
258 }
259 
260 #if defined(CONFIG_OF_BOARD_SETUP)
261 int ft_board_setup(void *blob, bd_t *bd)
262 {
263 	ft_cpu_setup(blob, bd);
264 
265 	FT_FSL_PCI_SETUP;
266 
267 	return 0;
268 }
269 #endif
270 
271 /*
272  * get_board_sys_clk
273  * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
274  */
275 
276 unsigned long
277 get_board_sys_clk(ulong dummy)
278 {
279 	u8 i;
280 	ulong val = 0;
281 	u8 *pixis_base = (u8 *)PIXIS_BASE;
282 
283 	i = in_8(pixis_base + PIXIS_SPD);
284 	i &= 0x07;
285 
286 	switch (i) {
287 	case 0:
288 		val = 33333000;
289 		break;
290 	case 1:
291 		val = 39999600;
292 		break;
293 	case 2:
294 		val = 49999500;
295 		break;
296 	case 3:
297 		val = 66666000;
298 		break;
299 	case 4:
300 		val = 83332500;
301 		break;
302 	case 5:
303 		val = 99999000;
304 		break;
305 	case 6:
306 		val = 133332000;
307 		break;
308 	case 7:
309 		val = 166665000;
310 		break;
311 	}
312 
313 	return val;
314 }
315 
316 int board_eth_init(bd_t *bis)
317 {
318 	return pci_eth_init(bis);
319 }
320 
321 void board_reset(void)
322 {
323 	u8 *pixis_base = (u8 *)PIXIS_BASE;
324 
325 	out_8(pixis_base + PIXIS_RST, 0);
326 
327 	while (1)
328 		;
329 }
330