1 /*
2  * Copyright 2008 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * Version 2 as published by the Free Software Foundation.
7  */
8 
9 #include <common.h>
10 #include <i2c.h>
11 
12 #include <asm/fsl_ddr_sdram.h>
13 
14 static void
15 get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
16 {
17 	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
18 }
19 
20 unsigned int fsl_ddr_get_mem_data_rate(void)
21 {
22 	return get_bus_freq(0);
23 }
24 
25 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
26 		      unsigned int ctrl_num)
27 {
28 	unsigned int i;
29 	unsigned int i2c_address = 0;
30 
31 	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
32 		if (ctrl_num == 0 && i == 0) {
33 			i2c_address = SPD_EEPROM_ADDRESS1;
34 		}
35 		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
36 	}
37 }
38 
39 void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
40 {
41 	/*
42 	 * Factors to consider for clock adjust:
43 	 *	- number of chips on bus
44 	 *	- position of slot
45 	 *	- DDR1 vs. DDR2?
46 	 *	- ???
47 	 *
48 	 * This needs to be determined on a board-by-board basis.
49 	 *	0110	3/4 cycle late
50 	 *	0111	7/8 cycle late
51 	 */
52 	popts->clk_adjust = 7;
53 
54 	/*
55 	 * Factors to consider for CPO:
56 	 *	- frequency
57 	 *	- ddr1 vs. ddr2
58 	 */
59 	popts->cpo_override = 10;
60 
61 	/*
62 	 * Factors to consider for write data delay:
63 	 *	- number of DIMMs
64 	 *
65 	 * 1 = 1/4 clock delay
66 	 * 2 = 1/2 clock delay
67 	 * 3 = 3/4 clock delay
68 	 * 4 = 1   clock delay
69 	 * 5 = 5/4 clock delay
70 	 * 6 = 3/2 clock delay
71 	 */
72 	popts->write_data_delay = 3;
73 
74 	/*
75 	 * Factors to consider for half-strength driver enable:
76 	 *	- number of DIMMs installed
77 	 */
78 	popts->half_strength_driver_enable = 0;
79 }
80