1 /*
2  * Copyright 2008 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * Version 2 as published by the Free Software Foundation.
7  */
8 
9 #include <common.h>
10 
11 #include <asm/fsl_ddr_sdram.h>
12 #include <asm/fsl_ddr_dimm_params.h>
13 
14 void fsl_ddr_board_options(memctl_options_t *popts,
15 				dimm_params_t *pdimm,
16 				unsigned int ctrl_num)
17 {
18 	/*
19 	 * Factors to consider for clock adjust:
20 	 *	- number of chips on bus
21 	 *	- position of slot
22 	 *	- DDR1 vs. DDR2?
23 	 *	- ???
24 	 *
25 	 * This needs to be determined on a board-by-board basis.
26 	 *	0110	3/4 cycle late
27 	 *	0111	7/8 cycle late
28 	 */
29 	popts->clk_adjust = 7;
30 
31 	/*
32 	 * Factors to consider for CPO:
33 	 *	- frequency
34 	 *	- ddr1 vs. ddr2
35 	 */
36 	popts->cpo_override = 10;
37 
38 	/*
39 	 * Factors to consider for write data delay:
40 	 *	- number of DIMMs
41 	 *
42 	 * 1 = 1/4 clock delay
43 	 * 2 = 1/2 clock delay
44 	 * 3 = 3/4 clock delay
45 	 * 4 = 1   clock delay
46 	 * 5 = 5/4 clock delay
47 	 * 6 = 3/2 clock delay
48 	 */
49 	popts->write_data_delay = 3;
50 
51 	/* 2T timing enable */
52 	popts->twot_en = 1;
53 
54 	/*
55 	 * Factors to consider for half-strength driver enable:
56 	 *	- number of DIMMs installed
57 	 */
58 	popts->half_strength_driver_enable = 0;
59 }
60