1 /* 2 * Copyright 2008-2010 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2000 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/mmu.h> 12 13 struct fsl_e_tlb_entry tlb_table[] = { 14 /* TLB 0 - for temp stack in cache */ 15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 16 MAS3_SX|MAS3_SW|MAS3_SR, 0, 17 0, 0, BOOKE_PAGESZ_4K, 0), 18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 19 MAS3_SX|MAS3_SW|MAS3_SR, 0, 20 0, 0, BOOKE_PAGESZ_4K, 0), 21 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 22 MAS3_SX|MAS3_SW|MAS3_SR, 0, 23 0, 0, BOOKE_PAGESZ_4K, 0), 24 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 25 MAS3_SX|MAS3_SW|MAS3_SR, 0, 26 0, 0, BOOKE_PAGESZ_4K, 0), 27 28 /* TLB 1 */ 29 /* *I*** - Covers boot page */ 30 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 31 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 32 0, 0, BOOKE_PAGESZ_4K, 1), 33 34 /* *I*G* - CCSRBAR */ 35 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 36 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 37 0, 1, BOOKE_PAGESZ_1M, 1), 38 39 /* W**G* - Flash/promjet, localbus */ 40 /* This will be changed to *I*G* after relocation to RAM. */ 41 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 42 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 43 0, 2, BOOKE_PAGESZ_256M, 1), 44 45 #ifndef CONFIG_NAND_SPL 46 /* *I*G* - PCI */ 47 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, 48 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 49 0, 3, BOOKE_PAGESZ_1G, 1), 50 51 /* *I*G* - PCI */ 52 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, 53 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 54 0, 4, BOOKE_PAGESZ_256M, 1), 55 56 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, 57 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 58 0, 5, BOOKE_PAGESZ_256M, 1), 59 60 /* *I*G* - PCI I/O */ 61 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, 62 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 63 0, 6, BOOKE_PAGESZ_256K, 1), 64 #endif 65 66 /* *I*G - NAND */ 67 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 68 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 69 0, 7, BOOKE_PAGESZ_1M, 1), 70 71 SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, 72 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 73 0, 8, BOOKE_PAGESZ_4K, 1), 74 75 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 76 /* *I*G - L2SRAM */ 77 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, 78 CONFIG_SYS_INIT_L2_ADDR_PHYS, 79 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 80 0, 9, BOOKE_PAGESZ_256K, 1), 81 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, 82 CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, 83 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 84 0, 10, BOOKE_PAGESZ_256K, 1), 85 #endif 86 }; 87 88 int num_tlb_entries = ARRAY_SIZE(tlb_table); 89