1 /* 2 * Copyright 2007-2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <miiphy.h> 34 #include <libfdt.h> 35 #include <fdt_support.h> 36 #include <tsec.h> 37 #include <netdev.h> 38 39 #include "../common/sgmii_riser.h" 40 41 long int fixed_sdram(void); 42 43 int checkboard (void) 44 { 45 u8 vboot; 46 u8 *pixis_base = (u8 *)PIXIS_BASE; 47 48 puts ("Board: MPC8572DS "); 49 #ifdef CONFIG_PHYS_64BIT 50 puts ("(36-bit addrmap) "); 51 #endif 52 printf ("Sys ID: 0x%02x, " 53 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 54 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 55 in_8(pixis_base + PIXIS_PVER)); 56 57 vboot = in_8(pixis_base + PIXIS_VBOOT); 58 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) { 59 case PIXIS_VBOOT_LBMAP_NOR0: 60 puts ("vBank: 0\n"); 61 break; 62 case PIXIS_VBOOT_LBMAP_PJET: 63 puts ("Promjet\n"); 64 break; 65 case PIXIS_VBOOT_LBMAP_NAND: 66 puts ("NAND\n"); 67 break; 68 case PIXIS_VBOOT_LBMAP_NOR1: 69 puts ("vBank: 1\n"); 70 break; 71 } 72 73 return 0; 74 } 75 76 phys_size_t initdram(int board_type) 77 { 78 phys_size_t dram_size = 0; 79 80 puts("Initializing...."); 81 82 #ifdef CONFIG_SPD_EEPROM 83 dram_size = fsl_ddr_sdram(); 84 #else 85 dram_size = fixed_sdram(); 86 #endif 87 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 88 dram_size *= 0x100000; 89 90 puts(" DDR: "); 91 return dram_size; 92 } 93 94 #if !defined(CONFIG_SPD_EEPROM) 95 /* 96 * Fixed sdram init -- doesn't use serial presence detect. 97 */ 98 99 phys_size_t fixed_sdram (void) 100 { 101 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 102 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 103 uint d_init; 104 105 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 106 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 107 108 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 109 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 110 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 111 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 112 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 113 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 114 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 115 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 116 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 117 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 118 119 #if defined (CONFIG_DDR_ECC) 120 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 121 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 122 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 123 #endif 124 asm("sync;isync"); 125 126 udelay(500); 127 128 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 129 130 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 131 d_init = 1; 132 debug("DDR - 1st controller: memory initializing\n"); 133 /* 134 * Poll until memory is initialized. 135 * 512 Meg at 400 might hit this 200 times or so. 136 */ 137 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 138 udelay(1000); 139 } 140 debug("DDR: memory initialized\n\n"); 141 asm("sync; isync"); 142 udelay(500); 143 #endif 144 145 return 512 * 1024 * 1024; 146 } 147 148 #endif 149 150 #ifdef CONFIG_PCIE1 151 static struct pci_controller pcie1_hose; 152 #endif 153 154 #ifdef CONFIG_PCIE2 155 static struct pci_controller pcie2_hose; 156 #endif 157 158 #ifdef CONFIG_PCIE3 159 static struct pci_controller pcie3_hose; 160 #endif 161 162 #ifdef CONFIG_PCI 163 void pci_init_board(void) 164 { 165 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 166 struct fsl_pci_info pci_info[3]; 167 u32 devdisr, pordevsr, io_sel, temp32; 168 int first_free_busno = 0; 169 int num = 0; 170 171 int pcie_ep, pcie_configured; 172 173 devdisr = in_be32(&gur->devdisr); 174 pordevsr = in_be32(&gur->pordevsr); 175 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 176 177 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 178 179 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 180 printf (" eTSEC1 is in sgmii mode.\n"); 181 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) 182 printf (" eTSEC2 is in sgmii mode.\n"); 183 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 184 printf (" eTSEC3 is in sgmii mode.\n"); 185 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) 186 printf (" eTSEC4 is in sgmii mode.\n"); 187 188 puts("\n"); 189 #ifdef CONFIG_PCIE3 190 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); 191 192 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ 193 SET_STD_PCIE_INFO(pci_info[num], 3); 194 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); 195 printf (" PCIE3 connected to ULI as %s (base addr %lx)\n", 196 pcie_ep ? "Endpoint" : "Root Complex", 197 pci_info[num].regs); 198 first_free_busno = fsl_pci_init_port(&pci_info[num++], 199 &pcie3_hose, first_free_busno); 200 /* 201 * Activate ULI1575 legacy chip by performing a fake 202 * memory access. Needed to make ULI RTC work. 203 * Device 1d has the first on-board memory BAR. 204 */ 205 pci_hose_read_config_dword(&pcie3_hose, PCI_BDF(2, 0x1d, 0), 206 PCI_BASE_ADDRESS_1, &temp32); 207 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { 208 void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0), 209 temp32, 4, 0); 210 debug(" uli1572 read to %p\n", p); 211 in_be32(p); 212 } 213 } else { 214 printf (" PCIE3: disabled\n"); 215 } 216 puts("\n"); 217 #else 218 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ 219 #endif 220 221 #ifdef CONFIG_PCIE2 222 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); 223 224 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ 225 SET_STD_PCIE_INFO(pci_info[num], 2); 226 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); 227 printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", 228 pcie_ep ? "Endpoint" : "Root Complex", 229 pci_info[num].regs); 230 first_free_busno = fsl_pci_init_port(&pci_info[num++], 231 &pcie2_hose, first_free_busno); 232 } else { 233 printf (" PCIE2: disabled\n"); 234 } 235 236 puts("\n"); 237 #else 238 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ 239 #endif 240 241 #ifdef CONFIG_PCIE1 242 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 243 244 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 245 SET_STD_PCIE_INFO(pci_info[num], 1); 246 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 247 printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", 248 pcie_ep ? "Endpoint" : "Root Complex", 249 pci_info[num].regs); 250 first_free_busno = fsl_pci_init_port(&pci_info[num++], 251 &pcie1_hose, first_free_busno); 252 } else { 253 printf (" PCIE1: disabled\n"); 254 } 255 256 puts("\n"); 257 #else 258 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 259 #endif 260 } 261 #endif 262 263 int board_early_init_r(void) 264 { 265 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 266 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 267 268 /* 269 * Remap Boot flash + PROMJET region to caching-inhibited 270 * so that flash can be erased properly. 271 */ 272 273 /* Flush d-cache and invalidate i-cache of any FLASH data */ 274 flush_dcache(); 275 invalidate_icache(); 276 277 /* invalidate existing TLB entry for flash + promjet */ 278 disable_tlb(flash_esel); 279 280 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 281 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 282 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 283 284 return 0; 285 } 286 287 #ifdef CONFIG_GET_CLK_FROM_ICS307 288 /* decode S[0-2] to Output Divider (OD) */ 289 static unsigned char ics307_S_to_OD[] = { 290 10, 2, 8, 4, 5, 7, 3, 6 291 }; 292 293 /* Calculate frequency being generated by ICS307-02 clock chip based upon 294 * the control bytes being programmed into it. */ 295 /* XXX: This function should probably go into a common library */ 296 static unsigned long 297 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) 298 { 299 const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ; 300 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 301 unsigned long RDW = cw2 & 0x7F; 302 unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; 303 unsigned long freq; 304 305 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ 306 307 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 308 * cw1: V8 V7 V6 V5 V4 V3 V2 V1 309 * cw2: V0 R6 R5 R4 R3 R2 R1 R0 310 * 311 * R6:R0 = Reference Divider Word (RDW) 312 * V8:V0 = VCO Divider Word (VDW) 313 * S2:S0 = Output Divider Select (OD) 314 * F1:F0 = Function of CLK2 Output 315 * TTL = duty cycle 316 * C1:C0 = internal load capacitance for cyrstal 317 */ 318 319 /* Adding 1 to get a "nicely" rounded number, but this needs 320 * more tweaking to get a "properly" rounded number. */ 321 322 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); 323 324 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, 325 freq); 326 return freq; 327 } 328 329 unsigned long get_board_sys_clk(ulong dummy) 330 { 331 u8 *pixis_base = (u8 *)PIXIS_BASE; 332 333 return ics307_clk_freq ( 334 in_8(pixis_base + PIXIS_VSYSCLK0), 335 in_8(pixis_base + PIXIS_VSYSCLK1), 336 in_8(pixis_base + PIXIS_VSYSCLK2) 337 ); 338 } 339 340 unsigned long get_board_ddr_clk(ulong dummy) 341 { 342 u8 *pixis_base = (u8 *)PIXIS_BASE; 343 344 return ics307_clk_freq ( 345 in_8(pixis_base + PIXIS_VDDRCLK0), 346 in_8(pixis_base + PIXIS_VDDRCLK1), 347 in_8(pixis_base + PIXIS_VDDRCLK2) 348 ); 349 } 350 #else 351 unsigned long get_board_sys_clk(ulong dummy) 352 { 353 u8 i; 354 ulong val = 0; 355 u8 *pixis_base = (u8 *)PIXIS_BASE; 356 357 i = in_8(pixis_base + PIXIS_SPD); 358 i &= 0x07; 359 360 switch (i) { 361 case 0: 362 val = 33333333; 363 break; 364 case 1: 365 val = 40000000; 366 break; 367 case 2: 368 val = 50000000; 369 break; 370 case 3: 371 val = 66666666; 372 break; 373 case 4: 374 val = 83333333; 375 break; 376 case 5: 377 val = 100000000; 378 break; 379 case 6: 380 val = 133333333; 381 break; 382 case 7: 383 val = 166666666; 384 break; 385 } 386 387 return val; 388 } 389 390 unsigned long get_board_ddr_clk(ulong dummy) 391 { 392 u8 i; 393 ulong val = 0; 394 u8 *pixis_base = (u8 *)PIXIS_BASE; 395 396 i = in_8(pixis_base + PIXIS_SPD); 397 i &= 0x38; 398 i >>= 3; 399 400 switch (i) { 401 case 0: 402 val = 33333333; 403 break; 404 case 1: 405 val = 40000000; 406 break; 407 case 2: 408 val = 50000000; 409 break; 410 case 3: 411 val = 66666666; 412 break; 413 case 4: 414 val = 83333333; 415 break; 416 case 5: 417 val = 100000000; 418 break; 419 case 6: 420 val = 133333333; 421 break; 422 case 7: 423 val = 166666666; 424 break; 425 } 426 return val; 427 } 428 #endif 429 430 #ifdef CONFIG_TSEC_ENET 431 int board_eth_init(bd_t *bis) 432 { 433 struct tsec_info_struct tsec_info[4]; 434 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 435 int num = 0; 436 437 #ifdef CONFIG_TSEC1 438 SET_STD_TSEC_INFO(tsec_info[num], 1); 439 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 440 tsec_info[num].flags |= TSEC_SGMII; 441 num++; 442 #endif 443 #ifdef CONFIG_TSEC2 444 SET_STD_TSEC_INFO(tsec_info[num], 2); 445 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) 446 tsec_info[num].flags |= TSEC_SGMII; 447 num++; 448 #endif 449 #ifdef CONFIG_TSEC3 450 SET_STD_TSEC_INFO(tsec_info[num], 3); 451 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 452 tsec_info[num].flags |= TSEC_SGMII; 453 num++; 454 #endif 455 #ifdef CONFIG_TSEC4 456 SET_STD_TSEC_INFO(tsec_info[num], 4); 457 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) 458 tsec_info[num].flags |= TSEC_SGMII; 459 num++; 460 #endif 461 462 if (!num) { 463 printf("No TSECs initialized\n"); 464 465 return 0; 466 } 467 468 #ifdef CONFIG_FSL_SGMII_RISER 469 fsl_sgmii_riser_init(tsec_info, num); 470 #endif 471 472 tsec_eth_init(bis, tsec_info, num); 473 474 return pci_eth_init(bis); 475 } 476 #endif 477 478 #if defined(CONFIG_OF_BOARD_SETUP) 479 void ft_board_setup(void *blob, bd_t *bd) 480 { 481 phys_addr_t base; 482 phys_size_t size; 483 484 ft_cpu_setup(blob, bd); 485 486 base = getenv_bootm_low(); 487 size = getenv_bootm_size(); 488 489 fdt_fixup_memory(blob, (u64)base, (u64)size); 490 491 #ifdef CONFIG_PCIE3 492 ft_fsl_pci_setup(blob, "pci0", &pcie3_hose); 493 #endif 494 #ifdef CONFIG_PCIE2 495 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); 496 #endif 497 #ifdef CONFIG_PCIE1 498 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); 499 #endif 500 #ifdef CONFIG_FSL_SGMII_RISER 501 fsl_sgmii_riser_fdt_fixup(blob); 502 #endif 503 } 504 #endif 505 506 #ifdef CONFIG_MP 507 extern void cpu_mp_lmb_reserve(struct lmb *lmb); 508 509 void board_lmb_reserve(struct lmb *lmb) 510 { 511 cpu_mp_lmb_reserve(lmb); 512 } 513 #endif 514