1 /* 2 * Copyright 2007-2008 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/immap_fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <miiphy.h> 34 #include <libfdt.h> 35 #include <fdt_support.h> 36 #include <tsec.h> 37 38 #include "../common/pixis.h" 39 #include "../common/sgmii_riser.h" 40 41 long int fixed_sdram(void); 42 43 int checkboard (void) 44 { 45 puts ("Board: MPC8572DS "); 46 #ifdef CONFIG_PHYS_64BIT 47 puts ("(36-bit addrmap) "); 48 #endif 49 printf ("Sys ID: 0x%02x, " 50 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n", 51 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), 52 in8(PIXIS_BASE + PIXIS_PVER)); 53 return 0; 54 } 55 56 phys_size_t initdram(int board_type) 57 { 58 phys_size_t dram_size = 0; 59 60 puts("Initializing...."); 61 62 #ifdef CONFIG_SPD_EEPROM 63 dram_size = fsl_ddr_sdram(); 64 #else 65 dram_size = fixed_sdram(); 66 #endif 67 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 68 dram_size *= 0x100000; 69 70 puts(" DDR: "); 71 return dram_size; 72 } 73 74 #if !defined(CONFIG_SPD_EEPROM) 75 /* 76 * Fixed sdram init -- doesn't use serial presence detect. 77 */ 78 79 phys_size_t fixed_sdram (void) 80 { 81 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 82 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 83 uint d_init; 84 85 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 86 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 87 88 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 89 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 90 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 91 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 92 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 93 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 94 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 95 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 96 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 97 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 98 99 #if defined (CONFIG_DDR_ECC) 100 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 101 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 102 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 103 #endif 104 asm("sync;isync"); 105 106 udelay(500); 107 108 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 109 110 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 111 d_init = 1; 112 debug("DDR - 1st controller: memory initializing\n"); 113 /* 114 * Poll until memory is initialized. 115 * 512 Meg at 400 might hit this 200 times or so. 116 */ 117 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 118 udelay(1000); 119 } 120 debug("DDR: memory initialized\n\n"); 121 asm("sync; isync"); 122 udelay(500); 123 #endif 124 125 return 512 * 1024 * 1024; 126 } 127 128 #endif 129 130 #ifdef CONFIG_PCIE1 131 static struct pci_controller pcie1_hose; 132 #endif 133 134 #ifdef CONFIG_PCIE2 135 static struct pci_controller pcie2_hose; 136 #endif 137 138 #ifdef CONFIG_PCIE3 139 static struct pci_controller pcie3_hose; 140 #endif 141 142 extern int fsl_pci_setup_inbound_windows(struct pci_region *r); 143 extern void fsl_pci_init(struct pci_controller *hose); 144 145 int first_free_busno=0; 146 #ifdef CONFIG_PCI 147 void pci_init_board(void) 148 { 149 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 150 uint devdisr = gur->devdisr; 151 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 152 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 153 154 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", 155 devdisr, io_sel, host_agent); 156 157 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 158 printf (" eTSEC1 is in sgmii mode.\n"); 159 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) 160 printf (" eTSEC2 is in sgmii mode.\n"); 161 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 162 printf (" eTSEC3 is in sgmii mode.\n"); 163 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) 164 printf (" eTSEC4 is in sgmii mode.\n"); 165 166 167 #ifdef CONFIG_PCIE3 168 { 169 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; 170 struct pci_controller *hose = &pcie3_hose; 171 int pcie_ep = (host_agent == 0) || (host_agent == 3) || 172 (host_agent == 5) || (host_agent == 6); 173 int pcie_configured = (io_sel == 0x7); 174 struct pci_region *r = hose->regions; 175 u32 temp32; 176 177 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ 178 printf ("\n PCIE3 connected to ULI as %s (base address %x)", 179 pcie_ep ? "End Point" : "Root Complex", 180 (uint)pci); 181 if (pci->pme_msg_det) { 182 pci->pme_msg_det = 0xffffffff; 183 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 184 } 185 printf ("\n"); 186 187 /* inbound */ 188 r += fsl_pci_setup_inbound_windows(r); 189 190 /* outbound memory */ 191 pci_set_region(r++, 192 CONFIG_SYS_PCIE3_MEM_BUS, 193 CONFIG_SYS_PCIE3_MEM_PHYS, 194 CONFIG_SYS_PCIE3_MEM_SIZE, 195 PCI_REGION_MEM); 196 197 /* outbound io */ 198 pci_set_region(r++, 199 CONFIG_SYS_PCIE3_IO_BUS, 200 CONFIG_SYS_PCIE3_IO_PHYS, 201 CONFIG_SYS_PCIE3_IO_SIZE, 202 PCI_REGION_IO); 203 204 hose->region_count = r - hose->regions; 205 hose->first_busno=first_free_busno; 206 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 207 208 fsl_pci_init(hose); 209 210 first_free_busno=hose->last_busno+1; 211 printf (" PCIE3 on bus %02x - %02x\n", 212 hose->first_busno,hose->last_busno); 213 214 /* 215 * Activate ULI1575 legacy chip by performing a fake 216 * memory access. Needed to make ULI RTC work. 217 * Device 1d has the first on-board memory BAR. 218 */ 219 220 pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ), 221 PCI_BASE_ADDRESS_1, &temp32); 222 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { 223 void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0), 224 temp32, 4, 0); 225 debug(" uli1572 read to %p\n", p); 226 in_be32(p); 227 } 228 } else { 229 printf (" PCIE3: disabled\n"); 230 } 231 232 } 233 #else 234 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ 235 #endif 236 237 #ifdef CONFIG_PCIE2 238 { 239 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; 240 struct pci_controller *hose = &pcie2_hose; 241 int pcie_ep = (host_agent == 2) || (host_agent == 4) || 242 (host_agent == 6) || (host_agent == 0); 243 int pcie_configured = (io_sel == 0x3) || (io_sel == 0x7); 244 struct pci_region *r = hose->regions; 245 246 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ 247 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", 248 pcie_ep ? "End Point" : "Root Complex", 249 (uint)pci); 250 if (pci->pme_msg_det) { 251 pci->pme_msg_det = 0xffffffff; 252 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 253 } 254 printf ("\n"); 255 256 /* inbound */ 257 r += fsl_pci_setup_inbound_windows(r); 258 259 /* outbound memory */ 260 pci_set_region(r++, 261 CONFIG_SYS_PCIE2_MEM_BUS, 262 CONFIG_SYS_PCIE2_MEM_PHYS, 263 CONFIG_SYS_PCIE2_MEM_SIZE, 264 PCI_REGION_MEM); 265 266 /* outbound io */ 267 pci_set_region(r++, 268 CONFIG_SYS_PCIE2_IO_BUS, 269 CONFIG_SYS_PCIE2_IO_PHYS, 270 CONFIG_SYS_PCIE2_IO_SIZE, 271 PCI_REGION_IO); 272 273 hose->region_count = r - hose->regions; 274 hose->first_busno=first_free_busno; 275 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 276 277 fsl_pci_init(hose); 278 first_free_busno=hose->last_busno+1; 279 printf (" PCIE2 on bus %02x - %02x\n", 280 hose->first_busno,hose->last_busno); 281 282 } else { 283 printf (" PCIE2: disabled\n"); 284 } 285 286 } 287 #else 288 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ 289 #endif 290 #ifdef CONFIG_PCIE1 291 { 292 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 293 struct pci_controller *hose = &pcie1_hose; 294 int pcie_ep = (host_agent <= 1) || (host_agent == 4) || 295 (host_agent == 5); 296 int pcie_configured = (io_sel == 0x2) || (io_sel == 0x3) || 297 (io_sel == 0x7) || (io_sel == 0xb) || 298 (io_sel == 0xc) || (io_sel == 0xf); 299 struct pci_region *r = hose->regions; 300 301 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 302 printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)", 303 pcie_ep ? "End Point" : "Root Complex", 304 (uint)pci); 305 if (pci->pme_msg_det) { 306 pci->pme_msg_det = 0xffffffff; 307 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 308 } 309 printf ("\n"); 310 311 /* inbound */ 312 r += fsl_pci_setup_inbound_windows(r); 313 314 /* outbound memory */ 315 pci_set_region(r++, 316 CONFIG_SYS_PCIE1_MEM_BUS, 317 CONFIG_SYS_PCIE1_MEM_PHYS, 318 CONFIG_SYS_PCIE1_MEM_SIZE, 319 PCI_REGION_MEM); 320 321 /* outbound io */ 322 pci_set_region(r++, 323 CONFIG_SYS_PCIE1_IO_BUS, 324 CONFIG_SYS_PCIE1_IO_PHYS, 325 CONFIG_SYS_PCIE1_IO_SIZE, 326 PCI_REGION_IO); 327 328 hose->region_count = r - hose->regions; 329 hose->first_busno=first_free_busno; 330 331 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 332 333 fsl_pci_init(hose); 334 335 first_free_busno=hose->last_busno+1; 336 printf(" PCIE1 on bus %02x - %02x\n", 337 hose->first_busno,hose->last_busno); 338 339 } else { 340 printf (" PCIE1: disabled\n"); 341 } 342 343 } 344 #else 345 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 346 #endif 347 } 348 #endif 349 350 int board_early_init_r(void) 351 { 352 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 353 const u8 flash_esel = 2; 354 355 /* 356 * Remap Boot flash + PROMJET region to caching-inhibited 357 * so that flash can be erased properly. 358 */ 359 360 /* Flush d-cache and invalidate i-cache of any FLASH data */ 361 flush_dcache(); 362 invalidate_icache(); 363 364 /* invalidate existing TLB entry for flash + promjet */ 365 disable_tlb(flash_esel); 366 367 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 368 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 369 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 370 371 return 0; 372 } 373 374 #ifdef CONFIG_GET_CLK_FROM_ICS307 375 /* decode S[0-2] to Output Divider (OD) */ 376 static unsigned char ics307_S_to_OD[] = { 377 10, 2, 8, 4, 5, 7, 3, 6 378 }; 379 380 /* Calculate frequency being generated by ICS307-02 clock chip based upon 381 * the control bytes being programmed into it. */ 382 /* XXX: This function should probably go into a common library */ 383 static unsigned long 384 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) 385 { 386 const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ; 387 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 388 unsigned long RDW = cw2 & 0x7F; 389 unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; 390 unsigned long freq; 391 392 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ 393 394 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 395 * cw1: V8 V7 V6 V5 V4 V3 V2 V1 396 * cw2: V0 R6 R5 R4 R3 R2 R1 R0 397 * 398 * R6:R0 = Reference Divider Word (RDW) 399 * V8:V0 = VCO Divider Word (VDW) 400 * S2:S0 = Output Divider Select (OD) 401 * F1:F0 = Function of CLK2 Output 402 * TTL = duty cycle 403 * C1:C0 = internal load capacitance for cyrstal 404 */ 405 406 /* Adding 1 to get a "nicely" rounded number, but this needs 407 * more tweaking to get a "properly" rounded number. */ 408 409 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); 410 411 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, 412 freq); 413 return freq; 414 } 415 416 unsigned long get_board_sys_clk(ulong dummy) 417 { 418 return ics307_clk_freq ( 419 in8(PIXIS_BASE + PIXIS_VSYSCLK0), 420 in8(PIXIS_BASE + PIXIS_VSYSCLK1), 421 in8(PIXIS_BASE + PIXIS_VSYSCLK2) 422 ); 423 } 424 425 unsigned long get_board_ddr_clk(ulong dummy) 426 { 427 return ics307_clk_freq ( 428 in8(PIXIS_BASE + PIXIS_VDDRCLK0), 429 in8(PIXIS_BASE + PIXIS_VDDRCLK1), 430 in8(PIXIS_BASE + PIXIS_VDDRCLK2) 431 ); 432 } 433 #else 434 unsigned long get_board_sys_clk(ulong dummy) 435 { 436 u8 i; 437 ulong val = 0; 438 439 i = in8(PIXIS_BASE + PIXIS_SPD); 440 i &= 0x07; 441 442 switch (i) { 443 case 0: 444 val = 33333333; 445 break; 446 case 1: 447 val = 40000000; 448 break; 449 case 2: 450 val = 50000000; 451 break; 452 case 3: 453 val = 66666666; 454 break; 455 case 4: 456 val = 83333333; 457 break; 458 case 5: 459 val = 100000000; 460 break; 461 case 6: 462 val = 133333333; 463 break; 464 case 7: 465 val = 166666666; 466 break; 467 } 468 469 return val; 470 } 471 472 unsigned long get_board_ddr_clk(ulong dummy) 473 { 474 u8 i; 475 ulong val = 0; 476 477 i = in8(PIXIS_BASE + PIXIS_SPD); 478 i &= 0x38; 479 i >>= 3; 480 481 switch (i) { 482 case 0: 483 val = 33333333; 484 break; 485 case 1: 486 val = 40000000; 487 break; 488 case 2: 489 val = 50000000; 490 break; 491 case 3: 492 val = 66666666; 493 break; 494 case 4: 495 val = 83333333; 496 break; 497 case 5: 498 val = 100000000; 499 break; 500 case 6: 501 val = 133333333; 502 break; 503 case 7: 504 val = 166666666; 505 break; 506 } 507 return val; 508 } 509 #endif 510 511 #ifdef CONFIG_TSEC_ENET 512 int board_eth_init(bd_t *bis) 513 { 514 struct tsec_info_struct tsec_info[4]; 515 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 516 int num = 0; 517 518 #ifdef CONFIG_TSEC1 519 SET_STD_TSEC_INFO(tsec_info[num], 1); 520 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 521 tsec_info[num].flags |= TSEC_SGMII; 522 num++; 523 #endif 524 #ifdef CONFIG_TSEC2 525 SET_STD_TSEC_INFO(tsec_info[num], 2); 526 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) 527 tsec_info[num].flags |= TSEC_SGMII; 528 num++; 529 #endif 530 #ifdef CONFIG_TSEC3 531 SET_STD_TSEC_INFO(tsec_info[num], 3); 532 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 533 tsec_info[num].flags |= TSEC_SGMII; 534 num++; 535 #endif 536 #ifdef CONFIG_TSEC4 537 SET_STD_TSEC_INFO(tsec_info[num], 4); 538 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) 539 tsec_info[num].flags |= TSEC_SGMII; 540 num++; 541 #endif 542 543 if (!num) { 544 printf("No TSECs initialized\n"); 545 546 return 0; 547 } 548 549 #ifdef CONFIG_FSL_SGMII_RISER 550 fsl_sgmii_riser_init(tsec_info, num); 551 #endif 552 553 tsec_eth_init(bis, tsec_info, num); 554 555 return 0; 556 } 557 #endif 558 559 #if defined(CONFIG_OF_BOARD_SETUP) 560 extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, 561 struct pci_controller *hose); 562 563 void ft_board_setup(void *blob, bd_t *bd) 564 { 565 phys_addr_t base; 566 phys_size_t size; 567 568 ft_cpu_setup(blob, bd); 569 570 base = getenv_bootm_low(); 571 size = getenv_bootm_size(); 572 573 fdt_fixup_memory(blob, (u64)base, (u64)size); 574 575 #ifdef CONFIG_PCIE3 576 ft_fsl_pci_setup(blob, "pci0", &pcie3_hose); 577 #endif 578 #ifdef CONFIG_PCIE2 579 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); 580 #endif 581 #ifdef CONFIG_PCIE1 582 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); 583 #endif 584 #ifdef CONFIG_FSL_SGMII_RISER 585 fsl_sgmii_riser_fdt_fixup(blob); 586 #endif 587 } 588 #endif 589 590 #ifdef CONFIG_MP 591 extern void cpu_mp_lmb_reserve(struct lmb *lmb); 592 593 void board_lmb_reserve(struct lmb *lmb) 594 { 595 cpu_mp_lmb_reserve(lmb); 596 } 597 #endif 598