1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <command.h> 9 #include <pci.h> 10 #include <asm/processor.h> 11 #include <asm/mmu.h> 12 #include <asm/cache.h> 13 #include <asm/immap_85xx.h> 14 #include <asm/fsl_pci.h> 15 #include <fsl_ddr_sdram.h> 16 #include <asm/io.h> 17 #include <asm/fsl_serdes.h> 18 #include <miiphy.h> 19 #include <linux/libfdt.h> 20 #include <fdt_support.h> 21 #include <tsec.h> 22 #include <fsl_mdio.h> 23 #include <netdev.h> 24 25 #include "../common/sgmii_riser.h" 26 27 int checkboard (void) 28 { 29 u8 vboot; 30 u8 *pixis_base = (u8 *)PIXIS_BASE; 31 32 printf("Board: MPC8572DS Sys ID: 0x%02x, " 33 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 34 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 35 in_8(pixis_base + PIXIS_PVER)); 36 37 vboot = in_8(pixis_base + PIXIS_VBOOT); 38 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) { 39 case PIXIS_VBOOT_LBMAP_NOR0: 40 puts ("vBank: 0\n"); 41 break; 42 case PIXIS_VBOOT_LBMAP_PJET: 43 puts ("Promjet\n"); 44 break; 45 case PIXIS_VBOOT_LBMAP_NAND: 46 puts ("NAND\n"); 47 break; 48 case PIXIS_VBOOT_LBMAP_NOR1: 49 puts ("vBank: 1\n"); 50 break; 51 } 52 53 return 0; 54 } 55 56 57 #if !defined(CONFIG_SPD_EEPROM) 58 /* 59 * Fixed sdram init -- doesn't use serial presence detect. 60 */ 61 62 phys_size_t fixed_sdram (void) 63 { 64 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 65 struct ccsr_ddr __iomem *ddr = &immap->im_ddr; 66 uint d_init; 67 68 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 69 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 70 71 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 72 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 73 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 74 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 75 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 76 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 77 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 78 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 79 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 80 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 81 82 #if defined (CONFIG_DDR_ECC) 83 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 84 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 85 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 86 #endif 87 asm("sync;isync"); 88 89 udelay(500); 90 91 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 92 93 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 94 d_init = 1; 95 debug("DDR - 1st controller: memory initializing\n"); 96 /* 97 * Poll until memory is initialized. 98 * 512 Meg at 400 might hit this 200 times or so. 99 */ 100 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 101 udelay(1000); 102 } 103 debug("DDR: memory initialized\n\n"); 104 asm("sync; isync"); 105 udelay(500); 106 #endif 107 108 return 512 * 1024 * 1024; 109 } 110 111 #endif 112 113 #ifdef CONFIG_PCI 114 void pci_init_board(void) 115 { 116 struct pci_controller *hose; 117 118 fsl_pcie_init_board(0); 119 120 hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR)); 121 122 if (hose) { 123 u32 temp32; 124 u8 uli_busno = hose->first_busno + 2; 125 126 /* 127 * Activate ULI1575 legacy chip by performing a fake 128 * memory access. Needed to make ULI RTC work. 129 * Device 1d has the first on-board memory BAR. 130 */ 131 pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0), 132 PCI_BASE_ADDRESS_1, &temp32); 133 134 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { 135 void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0), 136 temp32, 4, 0); 137 debug(" uli1572 read to %p\n", p); 138 in_be32(p); 139 } 140 } 141 } 142 #endif 143 144 int board_early_init_r(void) 145 { 146 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 147 int flash_esel = find_tlb_idx((void *)flashbase, 1); 148 149 /* 150 * Remap Boot flash + PROMJET region to caching-inhibited 151 * so that flash can be erased properly. 152 */ 153 154 /* Flush d-cache and invalidate i-cache of any FLASH data */ 155 flush_dcache(); 156 invalidate_icache(); 157 158 if (flash_esel == -1) { 159 /* very unlikely unless something is messed up */ 160 puts("Error: Could not find TLB for FLASH BASE\n"); 161 flash_esel = 2; /* give our best effort to continue */ 162 } else { 163 /* invalidate existing TLB entry for flash + promjet */ 164 disable_tlb(flash_esel); 165 } 166 167 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 168 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 169 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 170 171 return 0; 172 } 173 174 int board_eth_init(bd_t *bis) 175 { 176 #ifdef CONFIG_TSEC_ENET 177 struct fsl_pq_mdio_info mdio_info; 178 struct tsec_info_struct tsec_info[4]; 179 int num = 0; 180 181 #ifdef CONFIG_TSEC1 182 SET_STD_TSEC_INFO(tsec_info[num], 1); 183 if (is_serdes_configured(SGMII_TSEC1)) { 184 puts("eTSEC1 is in sgmii mode.\n"); 185 tsec_info[num].flags |= TSEC_SGMII; 186 } 187 num++; 188 #endif 189 #ifdef CONFIG_TSEC2 190 SET_STD_TSEC_INFO(tsec_info[num], 2); 191 if (is_serdes_configured(SGMII_TSEC2)) { 192 puts("eTSEC2 is in sgmii mode.\n"); 193 tsec_info[num].flags |= TSEC_SGMII; 194 } 195 num++; 196 #endif 197 #ifdef CONFIG_TSEC3 198 SET_STD_TSEC_INFO(tsec_info[num], 3); 199 if (is_serdes_configured(SGMII_TSEC3)) { 200 puts("eTSEC3 is in sgmii mode.\n"); 201 tsec_info[num].flags |= TSEC_SGMII; 202 } 203 num++; 204 #endif 205 #ifdef CONFIG_TSEC4 206 SET_STD_TSEC_INFO(tsec_info[num], 4); 207 if (is_serdes_configured(SGMII_TSEC4)) { 208 puts("eTSEC4 is in sgmii mode.\n"); 209 tsec_info[num].flags |= TSEC_SGMII; 210 } 211 num++; 212 #endif 213 214 if (!num) { 215 printf("No TSECs initialized\n"); 216 217 return 0; 218 } 219 220 #ifdef CONFIG_FSL_SGMII_RISER 221 fsl_sgmii_riser_init(tsec_info, num); 222 #endif 223 224 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 225 mdio_info.name = DEFAULT_MII_NAME; 226 fsl_pq_mdio_init(bis, &mdio_info); 227 228 tsec_eth_init(bis, tsec_info, num); 229 #endif 230 231 return pci_eth_init(bis); 232 } 233 234 #if defined(CONFIG_OF_BOARD_SETUP) 235 int ft_board_setup(void *blob, bd_t *bd) 236 { 237 phys_addr_t base; 238 phys_size_t size; 239 240 ft_cpu_setup(blob, bd); 241 242 base = env_get_bootm_low(); 243 size = env_get_bootm_size(); 244 245 fdt_fixup_memory(blob, (u64)base, (u64)size); 246 247 FT_FSL_PCI_SETUP; 248 249 #ifdef CONFIG_FSL_SGMII_RISER 250 fsl_sgmii_riser_fdt_fixup(blob); 251 #endif 252 253 return 0; 254 } 255 #endif 256