1 /* 2 * Copyright 2007-2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <miiphy.h> 34 #include <libfdt.h> 35 #include <fdt_support.h> 36 #include <tsec.h> 37 #include <netdev.h> 38 39 #include "../common/pixis.h" 40 #include "../common/sgmii_riser.h" 41 42 long int fixed_sdram(void); 43 44 int checkboard (void) 45 { 46 u8 vboot; 47 u8 *pixis_base = (u8 *)PIXIS_BASE; 48 49 puts ("Board: MPC8572DS "); 50 #ifdef CONFIG_PHYS_64BIT 51 puts ("(36-bit addrmap) "); 52 #endif 53 printf ("Sys ID: 0x%02x, " 54 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 55 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 56 in_8(pixis_base + PIXIS_PVER)); 57 58 vboot = in_8(pixis_base + PIXIS_VBOOT); 59 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) { 60 case PIXIS_VBOOT_LBMAP_NOR0: 61 puts ("vBank: 0\n"); 62 break; 63 case PIXIS_VBOOT_LBMAP_PJET: 64 puts ("Promjet\n"); 65 break; 66 case PIXIS_VBOOT_LBMAP_NAND: 67 puts ("NAND\n"); 68 break; 69 case PIXIS_VBOOT_LBMAP_NOR1: 70 puts ("vBank: 1\n"); 71 break; 72 } 73 74 return 0; 75 } 76 77 phys_size_t initdram(int board_type) 78 { 79 phys_size_t dram_size = 0; 80 81 puts("Initializing...."); 82 83 #ifdef CONFIG_SPD_EEPROM 84 dram_size = fsl_ddr_sdram(); 85 #else 86 dram_size = fixed_sdram(); 87 #endif 88 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 89 dram_size *= 0x100000; 90 91 puts(" DDR: "); 92 return dram_size; 93 } 94 95 #if !defined(CONFIG_SPD_EEPROM) 96 /* 97 * Fixed sdram init -- doesn't use serial presence detect. 98 */ 99 100 phys_size_t fixed_sdram (void) 101 { 102 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 103 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 104 uint d_init; 105 106 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 107 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 108 109 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 110 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 111 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 112 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 113 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 114 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 115 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 116 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 117 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 118 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 119 120 #if defined (CONFIG_DDR_ECC) 121 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 122 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 123 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 124 #endif 125 asm("sync;isync"); 126 127 udelay(500); 128 129 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 130 131 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 132 d_init = 1; 133 debug("DDR - 1st controller: memory initializing\n"); 134 /* 135 * Poll until memory is initialized. 136 * 512 Meg at 400 might hit this 200 times or so. 137 */ 138 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 139 udelay(1000); 140 } 141 debug("DDR: memory initialized\n\n"); 142 asm("sync; isync"); 143 udelay(500); 144 #endif 145 146 return 512 * 1024 * 1024; 147 } 148 149 #endif 150 151 #ifdef CONFIG_PCIE1 152 static struct pci_controller pcie1_hose; 153 #endif 154 155 #ifdef CONFIG_PCIE2 156 static struct pci_controller pcie2_hose; 157 #endif 158 159 #ifdef CONFIG_PCIE3 160 static struct pci_controller pcie3_hose; 161 #endif 162 163 #ifdef CONFIG_PCI 164 void pci_init_board(void) 165 { 166 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 167 struct fsl_pci_info pci_info[3]; 168 u32 devdisr, pordevsr, io_sel, temp32; 169 int first_free_busno = 0; 170 int num = 0; 171 172 int pcie_ep, pcie_configured; 173 174 devdisr = in_be32(&gur->devdisr); 175 pordevsr = in_be32(&gur->pordevsr); 176 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 177 178 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 179 180 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 181 printf (" eTSEC1 is in sgmii mode.\n"); 182 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) 183 printf (" eTSEC2 is in sgmii mode.\n"); 184 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 185 printf (" eTSEC3 is in sgmii mode.\n"); 186 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) 187 printf (" eTSEC4 is in sgmii mode.\n"); 188 189 puts("\n"); 190 #ifdef CONFIG_PCIE3 191 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); 192 193 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ 194 SET_STD_PCIE_INFO(pci_info[num], 3); 195 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); 196 printf (" PCIE3 connected to ULI as %s (base addr %lx)\n", 197 pcie_ep ? "Endpoint" : "Root Complex", 198 pci_info[num].regs); 199 first_free_busno = fsl_pci_init_port(&pci_info[num++], 200 &pcie3_hose, first_free_busno); 201 /* 202 * Activate ULI1575 legacy chip by performing a fake 203 * memory access. Needed to make ULI RTC work. 204 * Device 1d has the first on-board memory BAR. 205 */ 206 pci_hose_read_config_dword(&pcie3_hose, PCI_BDF(2, 0x1d, 0), 207 PCI_BASE_ADDRESS_1, &temp32); 208 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { 209 void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0), 210 temp32, 4, 0); 211 debug(" uli1572 read to %p\n", p); 212 in_be32(p); 213 } 214 } else { 215 printf (" PCIE3: disabled\n"); 216 } 217 puts("\n"); 218 #else 219 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ 220 #endif 221 222 #ifdef CONFIG_PCIE2 223 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); 224 225 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ 226 SET_STD_PCIE_INFO(pci_info[num], 2); 227 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); 228 printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", 229 pcie_ep ? "Endpoint" : "Root Complex", 230 pci_info[num].regs); 231 first_free_busno = fsl_pci_init_port(&pci_info[num++], 232 &pcie2_hose, first_free_busno); 233 } else { 234 printf (" PCIE2: disabled\n"); 235 } 236 237 puts("\n"); 238 #else 239 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ 240 #endif 241 242 #ifdef CONFIG_PCIE1 243 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 244 245 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 246 SET_STD_PCIE_INFO(pci_info[num], 1); 247 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 248 printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", 249 pcie_ep ? "Endpoint" : "Root Complex", 250 pci_info[num].regs); 251 first_free_busno = fsl_pci_init_port(&pci_info[num++], 252 &pcie1_hose, first_free_busno); 253 } else { 254 printf (" PCIE1: disabled\n"); 255 } 256 257 puts("\n"); 258 #else 259 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 260 #endif 261 } 262 #endif 263 264 int board_early_init_r(void) 265 { 266 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 267 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 268 269 /* 270 * Remap Boot flash + PROMJET region to caching-inhibited 271 * so that flash can be erased properly. 272 */ 273 274 /* Flush d-cache and invalidate i-cache of any FLASH data */ 275 flush_dcache(); 276 invalidate_icache(); 277 278 /* invalidate existing TLB entry for flash + promjet */ 279 disable_tlb(flash_esel); 280 281 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 282 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 283 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 284 285 return 0; 286 } 287 288 #ifdef CONFIG_GET_CLK_FROM_ICS307 289 /* decode S[0-2] to Output Divider (OD) */ 290 static unsigned char ics307_S_to_OD[] = { 291 10, 2, 8, 4, 5, 7, 3, 6 292 }; 293 294 /* Calculate frequency being generated by ICS307-02 clock chip based upon 295 * the control bytes being programmed into it. */ 296 /* XXX: This function should probably go into a common library */ 297 static unsigned long 298 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) 299 { 300 const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ; 301 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 302 unsigned long RDW = cw2 & 0x7F; 303 unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; 304 unsigned long freq; 305 306 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ 307 308 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 309 * cw1: V8 V7 V6 V5 V4 V3 V2 V1 310 * cw2: V0 R6 R5 R4 R3 R2 R1 R0 311 * 312 * R6:R0 = Reference Divider Word (RDW) 313 * V8:V0 = VCO Divider Word (VDW) 314 * S2:S0 = Output Divider Select (OD) 315 * F1:F0 = Function of CLK2 Output 316 * TTL = duty cycle 317 * C1:C0 = internal load capacitance for cyrstal 318 */ 319 320 /* Adding 1 to get a "nicely" rounded number, but this needs 321 * more tweaking to get a "properly" rounded number. */ 322 323 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); 324 325 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, 326 freq); 327 return freq; 328 } 329 330 unsigned long get_board_sys_clk(ulong dummy) 331 { 332 u8 *pixis_base = (u8 *)PIXIS_BASE; 333 334 return ics307_clk_freq ( 335 in_8(pixis_base + PIXIS_VSYSCLK0), 336 in_8(pixis_base + PIXIS_VSYSCLK1), 337 in_8(pixis_base + PIXIS_VSYSCLK2) 338 ); 339 } 340 341 unsigned long get_board_ddr_clk(ulong dummy) 342 { 343 u8 *pixis_base = (u8 *)PIXIS_BASE; 344 345 return ics307_clk_freq ( 346 in_8(pixis_base + PIXIS_VDDRCLK0), 347 in_8(pixis_base + PIXIS_VDDRCLK1), 348 in_8(pixis_base + PIXIS_VDDRCLK2) 349 ); 350 } 351 #else 352 unsigned long get_board_sys_clk(ulong dummy) 353 { 354 u8 i; 355 ulong val = 0; 356 u8 *pixis_base = (u8 *)PIXIS_BASE; 357 358 i = in_8(pixis_base + PIXIS_SPD); 359 i &= 0x07; 360 361 switch (i) { 362 case 0: 363 val = 33333333; 364 break; 365 case 1: 366 val = 40000000; 367 break; 368 case 2: 369 val = 50000000; 370 break; 371 case 3: 372 val = 66666666; 373 break; 374 case 4: 375 val = 83333333; 376 break; 377 case 5: 378 val = 100000000; 379 break; 380 case 6: 381 val = 133333333; 382 break; 383 case 7: 384 val = 166666666; 385 break; 386 } 387 388 return val; 389 } 390 391 unsigned long get_board_ddr_clk(ulong dummy) 392 { 393 u8 i; 394 ulong val = 0; 395 u8 *pixis_base = (u8 *)PIXIS_BASE; 396 397 i = in_8(pixis_base + PIXIS_SPD); 398 i &= 0x38; 399 i >>= 3; 400 401 switch (i) { 402 case 0: 403 val = 33333333; 404 break; 405 case 1: 406 val = 40000000; 407 break; 408 case 2: 409 val = 50000000; 410 break; 411 case 3: 412 val = 66666666; 413 break; 414 case 4: 415 val = 83333333; 416 break; 417 case 5: 418 val = 100000000; 419 break; 420 case 6: 421 val = 133333333; 422 break; 423 case 7: 424 val = 166666666; 425 break; 426 } 427 return val; 428 } 429 #endif 430 431 #ifdef CONFIG_TSEC_ENET 432 int board_eth_init(bd_t *bis) 433 { 434 struct tsec_info_struct tsec_info[4]; 435 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 436 int num = 0; 437 438 #ifdef CONFIG_TSEC1 439 SET_STD_TSEC_INFO(tsec_info[num], 1); 440 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 441 tsec_info[num].flags |= TSEC_SGMII; 442 num++; 443 #endif 444 #ifdef CONFIG_TSEC2 445 SET_STD_TSEC_INFO(tsec_info[num], 2); 446 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) 447 tsec_info[num].flags |= TSEC_SGMII; 448 num++; 449 #endif 450 #ifdef CONFIG_TSEC3 451 SET_STD_TSEC_INFO(tsec_info[num], 3); 452 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 453 tsec_info[num].flags |= TSEC_SGMII; 454 num++; 455 #endif 456 #ifdef CONFIG_TSEC4 457 SET_STD_TSEC_INFO(tsec_info[num], 4); 458 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) 459 tsec_info[num].flags |= TSEC_SGMII; 460 num++; 461 #endif 462 463 if (!num) { 464 printf("No TSECs initialized\n"); 465 466 return 0; 467 } 468 469 #ifdef CONFIG_FSL_SGMII_RISER 470 fsl_sgmii_riser_init(tsec_info, num); 471 #endif 472 473 tsec_eth_init(bis, tsec_info, num); 474 475 return pci_eth_init(bis); 476 } 477 #endif 478 479 #if defined(CONFIG_OF_BOARD_SETUP) 480 void ft_board_setup(void *blob, bd_t *bd) 481 { 482 phys_addr_t base; 483 phys_size_t size; 484 485 ft_cpu_setup(blob, bd); 486 487 base = getenv_bootm_low(); 488 size = getenv_bootm_size(); 489 490 fdt_fixup_memory(blob, (u64)base, (u64)size); 491 492 #ifdef CONFIG_PCIE3 493 ft_fsl_pci_setup(blob, "pci0", &pcie3_hose); 494 #endif 495 #ifdef CONFIG_PCIE2 496 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); 497 #endif 498 #ifdef CONFIG_PCIE1 499 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); 500 #endif 501 #ifdef CONFIG_FSL_SGMII_RISER 502 fsl_sgmii_riser_fdt_fixup(blob); 503 #endif 504 } 505 #endif 506 507 #ifdef CONFIG_MP 508 extern void cpu_mp_lmb_reserve(struct lmb *lmb); 509 510 void board_lmb_reserve(struct lmb *lmb) 511 { 512 cpu_mp_lmb_reserve(lmb); 513 } 514 #endif 515