1 /* 2 * Copyright 2007-2008 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <miiphy.h> 34 #include <libfdt.h> 35 #include <fdt_support.h> 36 #include <tsec.h> 37 #include <netdev.h> 38 39 #include "../common/pixis.h" 40 #include "../common/sgmii_riser.h" 41 42 long int fixed_sdram(void); 43 44 int checkboard (void) 45 { 46 u8 vboot; 47 u8 *pixis_base = (u8 *)PIXIS_BASE; 48 49 puts ("Board: MPC8572DS "); 50 #ifdef CONFIG_PHYS_64BIT 51 puts ("(36-bit addrmap) "); 52 #endif 53 printf ("Sys ID: 0x%02x, " 54 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 55 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 56 in_8(pixis_base + PIXIS_PVER)); 57 58 vboot = in_8(pixis_base + PIXIS_VBOOT); 59 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) { 60 case PIXIS_VBOOT_LBMAP_NOR0: 61 puts ("vBank: 0\n"); 62 break; 63 case PIXIS_VBOOT_LBMAP_PJET: 64 puts ("Promjet\n"); 65 break; 66 case PIXIS_VBOOT_LBMAP_NAND: 67 puts ("NAND\n"); 68 break; 69 case PIXIS_VBOOT_LBMAP_NOR1: 70 puts ("vBank: 1\n"); 71 break; 72 } 73 74 return 0; 75 } 76 77 phys_size_t initdram(int board_type) 78 { 79 phys_size_t dram_size = 0; 80 81 puts("Initializing...."); 82 83 #ifdef CONFIG_SPD_EEPROM 84 dram_size = fsl_ddr_sdram(); 85 #else 86 dram_size = fixed_sdram(); 87 #endif 88 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 89 dram_size *= 0x100000; 90 91 puts(" DDR: "); 92 return dram_size; 93 } 94 95 #if !defined(CONFIG_SPD_EEPROM) 96 /* 97 * Fixed sdram init -- doesn't use serial presence detect. 98 */ 99 100 phys_size_t fixed_sdram (void) 101 { 102 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 103 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 104 uint d_init; 105 106 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 107 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 108 109 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 110 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 111 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 112 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 113 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 114 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 115 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 116 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 117 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 118 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 119 120 #if defined (CONFIG_DDR_ECC) 121 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 122 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 123 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 124 #endif 125 asm("sync;isync"); 126 127 udelay(500); 128 129 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 130 131 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 132 d_init = 1; 133 debug("DDR - 1st controller: memory initializing\n"); 134 /* 135 * Poll until memory is initialized. 136 * 512 Meg at 400 might hit this 200 times or so. 137 */ 138 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 139 udelay(1000); 140 } 141 debug("DDR: memory initialized\n\n"); 142 asm("sync; isync"); 143 udelay(500); 144 #endif 145 146 return 512 * 1024 * 1024; 147 } 148 149 #endif 150 151 #ifdef CONFIG_PCIE1 152 static struct pci_controller pcie1_hose; 153 #endif 154 155 #ifdef CONFIG_PCIE2 156 static struct pci_controller pcie2_hose; 157 #endif 158 159 #ifdef CONFIG_PCIE3 160 static struct pci_controller pcie3_hose; 161 #endif 162 163 #ifdef CONFIG_PCI 164 void pci_init_board(void) 165 { 166 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 167 struct fsl_pci_info pci_info[3]; 168 u32 devdisr, pordevsr, io_sel, host_agent, temp32; 169 int first_free_busno = 0; 170 int num = 0; 171 172 int pcie_ep, pcie_configured; 173 174 devdisr = in_be32(&gur->devdisr); 175 pordevsr = in_be32(&gur->pordevsr); 176 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 177 host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16; 178 179 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", 180 devdisr, io_sel, host_agent); 181 182 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 183 printf (" eTSEC1 is in sgmii mode.\n"); 184 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) 185 printf (" eTSEC2 is in sgmii mode.\n"); 186 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 187 printf (" eTSEC3 is in sgmii mode.\n"); 188 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) 189 printf (" eTSEC4 is in sgmii mode.\n"); 190 191 puts("\n"); 192 #ifdef CONFIG_PCIE3 193 pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); 194 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); 195 196 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ 197 SET_STD_PCIE_INFO(pci_info[num], 3); 198 printf (" PCIE3 connected to ULI as %s (base addr %lx)\n", 199 pcie_ep ? "End Point" : "Root Complex", 200 pci_info[num].regs); 201 first_free_busno = fsl_pci_init_port(&pci_info[num++], 202 &pcie3_hose, first_free_busno); 203 /* 204 * Activate ULI1575 legacy chip by performing a fake 205 * memory access. Needed to make ULI RTC work. 206 * Device 1d has the first on-board memory BAR. 207 */ 208 pci_hose_read_config_dword(&pcie3_hose, PCI_BDF(2, 0x1d, 0), 209 PCI_BASE_ADDRESS_1, &temp32); 210 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { 211 void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0), 212 temp32, 4, 0); 213 debug(" uli1572 read to %p\n", p); 214 in_be32(p); 215 } 216 } else { 217 printf (" PCIE3: disabled\n"); 218 } 219 puts("\n"); 220 #else 221 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ 222 #endif 223 224 #ifdef CONFIG_PCIE2 225 pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); 226 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); 227 228 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ 229 SET_STD_PCIE_INFO(pci_info[num], 2); 230 printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", 231 pcie_ep ? "End Point" : "Root Complex", 232 pci_info[num].regs); 233 first_free_busno = fsl_pci_init_port(&pci_info[num++], 234 &pcie2_hose, first_free_busno); 235 } else { 236 printf (" PCIE2: disabled\n"); 237 } 238 239 puts("\n"); 240 #else 241 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ 242 #endif 243 244 #ifdef CONFIG_PCIE1 245 pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); 246 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 247 248 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 249 SET_STD_PCIE_INFO(pci_info[num], 1); 250 printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", 251 pcie_ep ? "End Point" : "Root Complex", 252 pci_info[num].regs); 253 first_free_busno = fsl_pci_init_port(&pci_info[num++], 254 &pcie1_hose, first_free_busno); 255 } else { 256 printf (" PCIE1: disabled\n"); 257 } 258 259 puts("\n"); 260 #else 261 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 262 #endif 263 } 264 #endif 265 266 int board_early_init_r(void) 267 { 268 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 269 const u8 flash_esel = 2; 270 271 /* 272 * Remap Boot flash + PROMJET region to caching-inhibited 273 * so that flash can be erased properly. 274 */ 275 276 /* Flush d-cache and invalidate i-cache of any FLASH data */ 277 flush_dcache(); 278 invalidate_icache(); 279 280 /* invalidate existing TLB entry for flash + promjet */ 281 disable_tlb(flash_esel); 282 283 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 284 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 285 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 286 287 return 0; 288 } 289 290 #ifdef CONFIG_GET_CLK_FROM_ICS307 291 /* decode S[0-2] to Output Divider (OD) */ 292 static unsigned char ics307_S_to_OD[] = { 293 10, 2, 8, 4, 5, 7, 3, 6 294 }; 295 296 /* Calculate frequency being generated by ICS307-02 clock chip based upon 297 * the control bytes being programmed into it. */ 298 /* XXX: This function should probably go into a common library */ 299 static unsigned long 300 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) 301 { 302 const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ; 303 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 304 unsigned long RDW = cw2 & 0x7F; 305 unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; 306 unsigned long freq; 307 308 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ 309 310 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 311 * cw1: V8 V7 V6 V5 V4 V3 V2 V1 312 * cw2: V0 R6 R5 R4 R3 R2 R1 R0 313 * 314 * R6:R0 = Reference Divider Word (RDW) 315 * V8:V0 = VCO Divider Word (VDW) 316 * S2:S0 = Output Divider Select (OD) 317 * F1:F0 = Function of CLK2 Output 318 * TTL = duty cycle 319 * C1:C0 = internal load capacitance for cyrstal 320 */ 321 322 /* Adding 1 to get a "nicely" rounded number, but this needs 323 * more tweaking to get a "properly" rounded number. */ 324 325 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); 326 327 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, 328 freq); 329 return freq; 330 } 331 332 unsigned long get_board_sys_clk(ulong dummy) 333 { 334 u8 *pixis_base = (u8 *)PIXIS_BASE; 335 336 return ics307_clk_freq ( 337 in_8(pixis_base + PIXIS_VSYSCLK0), 338 in_8(pixis_base + PIXIS_VSYSCLK1), 339 in_8(pixis_base + PIXIS_VSYSCLK2) 340 ); 341 } 342 343 unsigned long get_board_ddr_clk(ulong dummy) 344 { 345 u8 *pixis_base = (u8 *)PIXIS_BASE; 346 347 return ics307_clk_freq ( 348 in_8(pixis_base + PIXIS_VDDRCLK0), 349 in_8(pixis_base + PIXIS_VDDRCLK1), 350 in_8(pixis_base + PIXIS_VDDRCLK2) 351 ); 352 } 353 #else 354 unsigned long get_board_sys_clk(ulong dummy) 355 { 356 u8 i; 357 ulong val = 0; 358 u8 *pixis_base = (u8 *)PIXIS_BASE; 359 360 i = in_8(pixis_base + PIXIS_SPD); 361 i &= 0x07; 362 363 switch (i) { 364 case 0: 365 val = 33333333; 366 break; 367 case 1: 368 val = 40000000; 369 break; 370 case 2: 371 val = 50000000; 372 break; 373 case 3: 374 val = 66666666; 375 break; 376 case 4: 377 val = 83333333; 378 break; 379 case 5: 380 val = 100000000; 381 break; 382 case 6: 383 val = 133333333; 384 break; 385 case 7: 386 val = 166666666; 387 break; 388 } 389 390 return val; 391 } 392 393 unsigned long get_board_ddr_clk(ulong dummy) 394 { 395 u8 i; 396 ulong val = 0; 397 u8 *pixis_base = (u8 *)PIXIS_BASE; 398 399 i = in_8(pixis_base + PIXIS_SPD); 400 i &= 0x38; 401 i >>= 3; 402 403 switch (i) { 404 case 0: 405 val = 33333333; 406 break; 407 case 1: 408 val = 40000000; 409 break; 410 case 2: 411 val = 50000000; 412 break; 413 case 3: 414 val = 66666666; 415 break; 416 case 4: 417 val = 83333333; 418 break; 419 case 5: 420 val = 100000000; 421 break; 422 case 6: 423 val = 133333333; 424 break; 425 case 7: 426 val = 166666666; 427 break; 428 } 429 return val; 430 } 431 #endif 432 433 #ifdef CONFIG_TSEC_ENET 434 int board_eth_init(bd_t *bis) 435 { 436 struct tsec_info_struct tsec_info[4]; 437 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 438 int num = 0; 439 440 #ifdef CONFIG_TSEC1 441 SET_STD_TSEC_INFO(tsec_info[num], 1); 442 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 443 tsec_info[num].flags |= TSEC_SGMII; 444 num++; 445 #endif 446 #ifdef CONFIG_TSEC2 447 SET_STD_TSEC_INFO(tsec_info[num], 2); 448 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) 449 tsec_info[num].flags |= TSEC_SGMII; 450 num++; 451 #endif 452 #ifdef CONFIG_TSEC3 453 SET_STD_TSEC_INFO(tsec_info[num], 3); 454 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 455 tsec_info[num].flags |= TSEC_SGMII; 456 num++; 457 #endif 458 #ifdef CONFIG_TSEC4 459 SET_STD_TSEC_INFO(tsec_info[num], 4); 460 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) 461 tsec_info[num].flags |= TSEC_SGMII; 462 num++; 463 #endif 464 465 if (!num) { 466 printf("No TSECs initialized\n"); 467 468 return 0; 469 } 470 471 #ifdef CONFIG_FSL_SGMII_RISER 472 fsl_sgmii_riser_init(tsec_info, num); 473 #endif 474 475 tsec_eth_init(bis, tsec_info, num); 476 477 return pci_eth_init(bis); 478 } 479 #endif 480 481 #if defined(CONFIG_OF_BOARD_SETUP) 482 void ft_board_setup(void *blob, bd_t *bd) 483 { 484 phys_addr_t base; 485 phys_size_t size; 486 487 ft_cpu_setup(blob, bd); 488 489 base = getenv_bootm_low(); 490 size = getenv_bootm_size(); 491 492 fdt_fixup_memory(blob, (u64)base, (u64)size); 493 494 #ifdef CONFIG_PCIE3 495 ft_fsl_pci_setup(blob, "pci0", &pcie3_hose); 496 #endif 497 #ifdef CONFIG_PCIE2 498 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); 499 #endif 500 #ifdef CONFIG_PCIE1 501 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); 502 #endif 503 #ifdef CONFIG_FSL_SGMII_RISER 504 fsl_sgmii_riser_fdt_fixup(blob); 505 #endif 506 } 507 #endif 508 509 #ifdef CONFIG_MP 510 extern void cpu_mp_lmb_reserve(struct lmb *lmb); 511 512 void board_lmb_reserve(struct lmb *lmb) 513 { 514 cpu_mp_lmb_reserve(lmb); 515 } 516 #endif 517