1 /*
2  * Copyright 2007-2011 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <command.h>
9 #include <pci.h>
10 #include <asm/processor.h>
11 #include <asm/mmu.h>
12 #include <asm/cache.h>
13 #include <asm/immap_85xx.h>
14 #include <asm/fsl_pci.h>
15 #include <fsl_ddr_sdram.h>
16 #include <asm/io.h>
17 #include <asm/fsl_serdes.h>
18 #include <miiphy.h>
19 #include <libfdt.h>
20 #include <fdt_support.h>
21 #include <tsec.h>
22 #include <fsl_mdio.h>
23 #include <netdev.h>
24 
25 #include "../common/sgmii_riser.h"
26 
27 int checkboard (void)
28 {
29 	u8 vboot;
30 	u8 *pixis_base = (u8 *)PIXIS_BASE;
31 
32 	printf("Board: MPC8572DS Sys ID: 0x%02x, "
33 		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
34 		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
35 		in_8(pixis_base + PIXIS_PVER));
36 
37 	vboot = in_8(pixis_base + PIXIS_VBOOT);
38 	switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
39 		case PIXIS_VBOOT_LBMAP_NOR0:
40 			puts ("vBank: 0\n");
41 			break;
42 		case PIXIS_VBOOT_LBMAP_PJET:
43 			puts ("Promjet\n");
44 			break;
45 		case PIXIS_VBOOT_LBMAP_NAND:
46 			puts ("NAND\n");
47 			break;
48 		case PIXIS_VBOOT_LBMAP_NOR1:
49 			puts ("vBank: 1\n");
50 			break;
51 	}
52 
53 	return 0;
54 }
55 
56 
57 #if !defined(CONFIG_SPD_EEPROM)
58 /*
59  * Fixed sdram init -- doesn't use serial presence detect.
60  */
61 
62 phys_size_t fixed_sdram (void)
63 {
64 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
65 	struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
66 	uint d_init;
67 
68 	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
69 	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
70 
71 	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
72 	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
73 	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
74 	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
75 	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
76 	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
77 	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
78 	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
79 	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
80 	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
81 
82 #if defined (CONFIG_DDR_ECC)
83 	ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
84 	ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
85 	ddr->err_sbe = CONFIG_SYS_DDR_SBE;
86 #endif
87 	asm("sync;isync");
88 
89 	udelay(500);
90 
91 	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
92 
93 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
94 	d_init = 1;
95 	debug("DDR - 1st controller: memory initializing\n");
96 	/*
97 	 * Poll until memory is initialized.
98 	 * 512 Meg at 400 might hit this 200 times or so.
99 	 */
100 	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
101 		udelay(1000);
102 	}
103 	debug("DDR: memory initialized\n\n");
104 	asm("sync; isync");
105 	udelay(500);
106 #endif
107 
108 	return 512 * 1024 * 1024;
109 }
110 
111 #endif
112 
113 #ifdef CONFIG_PCI
114 void pci_init_board(void)
115 {
116 	struct pci_controller *hose;
117 
118 	fsl_pcie_init_board(0);
119 
120 	hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR));
121 
122 	if (hose) {
123 		u32 temp32;
124 		u8 uli_busno = hose->first_busno + 2;
125 
126 		/*
127 		 * Activate ULI1575 legacy chip by performing a fake
128 		 * memory access.  Needed to make ULI RTC work.
129 		 * Device 1d has the first on-board memory BAR.
130 		 */
131 		pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0),
132 				PCI_BASE_ADDRESS_1, &temp32);
133 
134 		if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
135 			void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0),
136 					temp32, 4, 0);
137 			debug(" uli1572 read to %p\n", p);
138 			in_be32(p);
139 		}
140 	}
141 }
142 #endif
143 
144 int board_early_init_r(void)
145 {
146 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
147 	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
148 
149 	/*
150 	 * Remap Boot flash + PROMJET region to caching-inhibited
151 	 * so that flash can be erased properly.
152 	 */
153 
154 	/* Flush d-cache and invalidate i-cache of any FLASH data */
155 	flush_dcache();
156 	invalidate_icache();
157 
158 	/* invalidate existing TLB entry for flash + promjet */
159 	disable_tlb(flash_esel);
160 
161 	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,	/* tlb, epn, rpn */
162 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
163 			0, flash_esel, BOOKE_PAGESZ_256M, 1);	/* ts, esel, tsize, iprot */
164 
165 	return 0;
166 }
167 
168 #ifdef CONFIG_TSEC_ENET
169 int board_eth_init(bd_t *bis)
170 {
171 	struct fsl_pq_mdio_info mdio_info;
172 	struct tsec_info_struct tsec_info[4];
173 	int num = 0;
174 
175 #ifdef CONFIG_TSEC1
176 	SET_STD_TSEC_INFO(tsec_info[num], 1);
177 	if (is_serdes_configured(SGMII_TSEC1)) {
178 		puts("eTSEC1 is in sgmii mode.\n");
179 		tsec_info[num].flags |= TSEC_SGMII;
180 	}
181 	num++;
182 #endif
183 #ifdef CONFIG_TSEC2
184 	SET_STD_TSEC_INFO(tsec_info[num], 2);
185 	if (is_serdes_configured(SGMII_TSEC2)) {
186 		puts("eTSEC2 is in sgmii mode.\n");
187 		tsec_info[num].flags |= TSEC_SGMII;
188 	}
189 	num++;
190 #endif
191 #ifdef CONFIG_TSEC3
192 	SET_STD_TSEC_INFO(tsec_info[num], 3);
193 	if (is_serdes_configured(SGMII_TSEC3)) {
194 		puts("eTSEC3 is in sgmii mode.\n");
195 		tsec_info[num].flags |= TSEC_SGMII;
196 	}
197 	num++;
198 #endif
199 #ifdef CONFIG_TSEC4
200 	SET_STD_TSEC_INFO(tsec_info[num], 4);
201 	if (is_serdes_configured(SGMII_TSEC4)) {
202 		puts("eTSEC4 is in sgmii mode.\n");
203 		tsec_info[num].flags |= TSEC_SGMII;
204 	}
205 	num++;
206 #endif
207 
208 	if (!num) {
209 		printf("No TSECs initialized\n");
210 
211 		return 0;
212 	}
213 
214 #ifdef CONFIG_FSL_SGMII_RISER
215 	fsl_sgmii_riser_init(tsec_info, num);
216 #endif
217 
218 	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
219 	mdio_info.name = DEFAULT_MII_NAME;
220 	fsl_pq_mdio_init(bis, &mdio_info);
221 
222 	tsec_eth_init(bis, tsec_info, num);
223 
224 	return pci_eth_init(bis);
225 }
226 #endif
227 
228 #if defined(CONFIG_OF_BOARD_SETUP)
229 void ft_board_setup(void *blob, bd_t *bd)
230 {
231 	phys_addr_t base;
232 	phys_size_t size;
233 
234 	ft_cpu_setup(blob, bd);
235 
236 	base = getenv_bootm_low();
237 	size = getenv_bootm_size();
238 
239 	fdt_fixup_memory(blob, (u64)base, (u64)size);
240 
241 	FT_FSL_PCI_SETUP;
242 
243 #ifdef CONFIG_FSL_SGMII_RISER
244 	fsl_sgmii_riser_fdt_fixup(blob);
245 #endif
246 }
247 #endif
248