1 /* 2 * Copyright 2007-2008 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/immap_fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <miiphy.h> 34 #include <libfdt.h> 35 #include <fdt_support.h> 36 #include <tsec.h> 37 38 #include "../common/pixis.h" 39 #include "../common/sgmii_riser.h" 40 41 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 42 extern void ddr_enable_ecc(unsigned int dram_size); 43 #endif 44 45 long int fixed_sdram(void); 46 47 int checkboard (void) 48 { 49 printf ("Board: MPC8572DS, System ID: 0x%02x, " 50 "System Version: 0x%02x, FPGA Version: 0x%02x\n", 51 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), 52 in8(PIXIS_BASE + PIXIS_PVER)); 53 return 0; 54 } 55 56 phys_size_t initdram(int board_type) 57 { 58 phys_size_t dram_size = 0; 59 60 puts("Initializing...."); 61 62 #ifdef CONFIG_SPD_EEPROM 63 dram_size = fsl_ddr_sdram(); 64 65 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 66 67 dram_size *= 0x100000; 68 #else 69 dram_size = fixed_sdram(); 70 #endif 71 72 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 73 /* 74 * Initialize and enable DDR ECC. 75 */ 76 ddr_enable_ecc(dram_size); 77 #endif 78 puts(" DDR: "); 79 return dram_size; 80 } 81 82 #if !defined(CONFIG_SPD_EEPROM) 83 /* 84 * Fixed sdram init -- doesn't use serial presence detect. 85 */ 86 87 phys_size_t fixed_sdram (void) 88 { 89 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 90 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 91 uint d_init; 92 93 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 94 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 95 96 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 97 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 98 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 99 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 100 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 101 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 102 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 103 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 104 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 105 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 106 107 #if defined (CONFIG_DDR_ECC) 108 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 109 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 110 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 111 #endif 112 asm("sync;isync"); 113 114 udelay(500); 115 116 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 117 118 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 119 d_init = 1; 120 debug("DDR - 1st controller: memory initializing\n"); 121 /* 122 * Poll until memory is initialized. 123 * 512 Meg at 400 might hit this 200 times or so. 124 */ 125 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 126 udelay(1000); 127 } 128 debug("DDR: memory initialized\n\n"); 129 asm("sync; isync"); 130 udelay(500); 131 #endif 132 133 return 512 * 1024 * 1024; 134 } 135 136 #endif 137 138 #ifdef CONFIG_PCIE1 139 static struct pci_controller pcie1_hose; 140 #endif 141 142 #ifdef CONFIG_PCIE2 143 static struct pci_controller pcie2_hose; 144 #endif 145 146 #ifdef CONFIG_PCIE3 147 static struct pci_controller pcie3_hose; 148 #endif 149 150 int first_free_busno=0; 151 #ifdef CONFIG_PCI 152 void pci_init_board(void) 153 { 154 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 155 uint devdisr = gur->devdisr; 156 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 157 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 158 159 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", 160 devdisr, io_sel, host_agent); 161 162 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 163 printf (" eTSEC1 is in sgmii mode.\n"); 164 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) 165 printf (" eTSEC2 is in sgmii mode.\n"); 166 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 167 printf (" eTSEC3 is in sgmii mode.\n"); 168 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) 169 printf (" eTSEC4 is in sgmii mode.\n"); 170 171 172 #ifdef CONFIG_PCIE3 173 { 174 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; 175 extern void fsl_pci_init(struct pci_controller *hose); 176 struct pci_controller *hose = &pcie3_hose; 177 int pcie_ep = (host_agent == 0) || (host_agent == 3) || 178 (host_agent == 5) || (host_agent == 6); 179 int pcie_configured = io_sel >= 1; 180 u32 temp32; 181 182 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 183 printf ("\n PCIE3 connected to ULI as %s (base address %x)", 184 pcie_ep ? "End Point" : "Root Complex", 185 (uint)pci); 186 if (pci->pme_msg_det) { 187 pci->pme_msg_det = 0xffffffff; 188 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 189 } 190 printf ("\n"); 191 192 /* inbound */ 193 pci_set_region(hose->regions + 0, 194 CONFIG_SYS_PCI_MEMORY_BUS, 195 CONFIG_SYS_PCI_MEMORY_PHYS, 196 CONFIG_SYS_PCI_MEMORY_SIZE, 197 PCI_REGION_MEM | PCI_REGION_MEMORY); 198 199 /* outbound memory */ 200 pci_set_region(hose->regions + 1, 201 CONFIG_SYS_PCIE3_MEM_BASE, 202 CONFIG_SYS_PCIE3_MEM_PHYS, 203 CONFIG_SYS_PCIE3_MEM_SIZE, 204 PCI_REGION_MEM); 205 206 /* outbound io */ 207 pci_set_region(hose->regions + 2, 208 CONFIG_SYS_PCIE3_IO_BASE, 209 CONFIG_SYS_PCIE3_IO_PHYS, 210 CONFIG_SYS_PCIE3_IO_SIZE, 211 PCI_REGION_IO); 212 213 hose->region_count = 3; 214 hose->first_busno=first_free_busno; 215 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 216 217 fsl_pci_init(hose); 218 219 first_free_busno=hose->last_busno+1; 220 printf (" PCIE3 on bus %02x - %02x\n", 221 hose->first_busno,hose->last_busno); 222 223 /* 224 * Activate ULI1575 legacy chip by performing a fake 225 * memory access. Needed to make ULI RTC work. 226 * Device 1d has the first on-board memory BAR. 227 */ 228 229 pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ), 230 PCI_BASE_ADDRESS_1, &temp32); 231 if (temp32 >= CONFIG_SYS_PCIE3_MEM_PHYS) { 232 debug(" uli1572 read to %x\n", temp32); 233 in_be32((unsigned *)temp32); 234 } 235 } else { 236 printf (" PCIE3: disabled\n"); 237 } 238 239 } 240 #else 241 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ 242 #endif 243 244 #ifdef CONFIG_PCIE2 245 { 246 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; 247 extern void fsl_pci_init(struct pci_controller *hose); 248 struct pci_controller *hose = &pcie2_hose; 249 int pcie_ep = (host_agent == 2) || (host_agent == 4) || 250 (host_agent == 6) || (host_agent == 0); 251 int pcie_configured = io_sel & 4; 252 253 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 254 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", 255 pcie_ep ? "End Point" : "Root Complex", 256 (uint)pci); 257 if (pci->pme_msg_det) { 258 pci->pme_msg_det = 0xffffffff; 259 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 260 } 261 printf ("\n"); 262 263 /* inbound */ 264 pci_set_region(hose->regions + 0, 265 CONFIG_SYS_PCI_MEMORY_BUS, 266 CONFIG_SYS_PCI_MEMORY_PHYS, 267 CONFIG_SYS_PCI_MEMORY_SIZE, 268 PCI_REGION_MEM | PCI_REGION_MEMORY); 269 270 /* outbound memory */ 271 pci_set_region(hose->regions + 1, 272 CONFIG_SYS_PCIE2_MEM_BASE, 273 CONFIG_SYS_PCIE2_MEM_PHYS, 274 CONFIG_SYS_PCIE2_MEM_SIZE, 275 PCI_REGION_MEM); 276 277 /* outbound io */ 278 pci_set_region(hose->regions + 2, 279 CONFIG_SYS_PCIE2_IO_BASE, 280 CONFIG_SYS_PCIE2_IO_PHYS, 281 CONFIG_SYS_PCIE2_IO_SIZE, 282 PCI_REGION_IO); 283 284 hose->region_count = 3; 285 hose->first_busno=first_free_busno; 286 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 287 288 fsl_pci_init(hose); 289 first_free_busno=hose->last_busno+1; 290 printf (" PCIE2 on bus %02x - %02x\n", 291 hose->first_busno,hose->last_busno); 292 293 } else { 294 printf (" PCIE2: disabled\n"); 295 } 296 297 } 298 #else 299 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ 300 #endif 301 #ifdef CONFIG_PCIE1 302 { 303 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 304 extern void fsl_pci_init(struct pci_controller *hose); 305 struct pci_controller *hose = &pcie1_hose; 306 int pcie_ep = (host_agent <= 1) || (host_agent == 4) || 307 (host_agent == 5); 308 int pcie_configured = io_sel & 6; 309 310 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 311 printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)", 312 pcie_ep ? "End Point" : "Root Complex", 313 (uint)pci); 314 if (pci->pme_msg_det) { 315 pci->pme_msg_det = 0xffffffff; 316 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 317 } 318 printf ("\n"); 319 320 /* inbound */ 321 pci_set_region(hose->regions + 0, 322 CONFIG_SYS_PCI_MEMORY_BUS, 323 CONFIG_SYS_PCI_MEMORY_PHYS, 324 CONFIG_SYS_PCI_MEMORY_SIZE, 325 PCI_REGION_MEM | PCI_REGION_MEMORY); 326 327 /* outbound memory */ 328 pci_set_region(hose->regions + 1, 329 CONFIG_SYS_PCIE1_MEM_BASE, 330 CONFIG_SYS_PCIE1_MEM_PHYS, 331 CONFIG_SYS_PCIE1_MEM_SIZE, 332 PCI_REGION_MEM); 333 334 /* outbound io */ 335 pci_set_region(hose->regions + 2, 336 CONFIG_SYS_PCIE1_IO_BASE, 337 CONFIG_SYS_PCIE1_IO_PHYS, 338 CONFIG_SYS_PCIE1_IO_SIZE, 339 PCI_REGION_IO); 340 341 hose->region_count = 3; 342 hose->first_busno=first_free_busno; 343 344 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 345 346 fsl_pci_init(hose); 347 348 first_free_busno=hose->last_busno+1; 349 printf(" PCIE1 on bus %02x - %02x\n", 350 hose->first_busno,hose->last_busno); 351 352 } else { 353 printf (" PCIE1: disabled\n"); 354 } 355 356 } 357 #else 358 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 359 #endif 360 } 361 #endif 362 363 int board_early_init_r(void) 364 { 365 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 366 const u8 flash_esel = 2; 367 368 /* 369 * Remap Boot flash + PROMJET region to caching-inhibited 370 * so that flash can be erased properly. 371 */ 372 373 /* Flush d-cache and invalidate i-cache of any FLASH data */ 374 flush_dcache(); 375 invalidate_icache(); 376 377 /* invalidate existing TLB entry for flash + promjet */ 378 disable_tlb(flash_esel); 379 380 set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */ 381 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 382 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 383 384 return 0; 385 } 386 387 #ifdef CONFIG_GET_CLK_FROM_ICS307 388 /* decode S[0-2] to Output Divider (OD) */ 389 static unsigned char ics307_S_to_OD[] = { 390 10, 2, 8, 4, 5, 7, 3, 6 391 }; 392 393 /* Calculate frequency being generated by ICS307-02 clock chip based upon 394 * the control bytes being programmed into it. */ 395 /* XXX: This function should probably go into a common library */ 396 static unsigned long 397 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) 398 { 399 const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ; 400 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 401 unsigned long RDW = cw2 & 0x7F; 402 unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; 403 unsigned long freq; 404 405 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ 406 407 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 408 * cw1: V8 V7 V6 V5 V4 V3 V2 V1 409 * cw2: V0 R6 R5 R4 R3 R2 R1 R0 410 * 411 * R6:R0 = Reference Divider Word (RDW) 412 * V8:V0 = VCO Divider Word (VDW) 413 * S2:S0 = Output Divider Select (OD) 414 * F1:F0 = Function of CLK2 Output 415 * TTL = duty cycle 416 * C1:C0 = internal load capacitance for cyrstal 417 */ 418 419 /* Adding 1 to get a "nicely" rounded number, but this needs 420 * more tweaking to get a "properly" rounded number. */ 421 422 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); 423 424 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, 425 freq); 426 return freq; 427 } 428 429 unsigned long get_board_sys_clk(ulong dummy) 430 { 431 return ics307_clk_freq ( 432 in8(PIXIS_BASE + PIXIS_VSYSCLK0), 433 in8(PIXIS_BASE + PIXIS_VSYSCLK1), 434 in8(PIXIS_BASE + PIXIS_VSYSCLK2) 435 ); 436 } 437 438 unsigned long get_board_ddr_clk(ulong dummy) 439 { 440 return ics307_clk_freq ( 441 in8(PIXIS_BASE + PIXIS_VDDRCLK0), 442 in8(PIXIS_BASE + PIXIS_VDDRCLK1), 443 in8(PIXIS_BASE + PIXIS_VDDRCLK2) 444 ); 445 } 446 #else 447 unsigned long get_board_sys_clk(ulong dummy) 448 { 449 u8 i; 450 ulong val = 0; 451 452 i = in8(PIXIS_BASE + PIXIS_SPD); 453 i &= 0x07; 454 455 switch (i) { 456 case 0: 457 val = 33333333; 458 break; 459 case 1: 460 val = 40000000; 461 break; 462 case 2: 463 val = 50000000; 464 break; 465 case 3: 466 val = 66666666; 467 break; 468 case 4: 469 val = 83333333; 470 break; 471 case 5: 472 val = 100000000; 473 break; 474 case 6: 475 val = 133333333; 476 break; 477 case 7: 478 val = 166666666; 479 break; 480 } 481 482 return val; 483 } 484 485 unsigned long get_board_ddr_clk(ulong dummy) 486 { 487 u8 i; 488 ulong val = 0; 489 490 i = in8(PIXIS_BASE + PIXIS_SPD); 491 i &= 0x38; 492 i >>= 3; 493 494 switch (i) { 495 case 0: 496 val = 33333333; 497 break; 498 case 1: 499 val = 40000000; 500 break; 501 case 2: 502 val = 50000000; 503 break; 504 case 3: 505 val = 66666666; 506 break; 507 case 4: 508 val = 83333333; 509 break; 510 case 5: 511 val = 100000000; 512 break; 513 case 6: 514 val = 133333333; 515 break; 516 case 7: 517 val = 166666666; 518 break; 519 } 520 return val; 521 } 522 #endif 523 524 #ifdef CONFIG_TSEC_ENET 525 int board_eth_init(bd_t *bis) 526 { 527 struct tsec_info_struct tsec_info[4]; 528 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 529 int num = 0; 530 531 #ifdef CONFIG_TSEC1 532 SET_STD_TSEC_INFO(tsec_info[num], 1); 533 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 534 tsec_info[num].flags |= TSEC_SGMII; 535 num++; 536 #endif 537 #ifdef CONFIG_TSEC2 538 SET_STD_TSEC_INFO(tsec_info[num], 2); 539 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) 540 tsec_info[num].flags |= TSEC_SGMII; 541 num++; 542 #endif 543 #ifdef CONFIG_TSEC3 544 SET_STD_TSEC_INFO(tsec_info[num], 3); 545 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 546 tsec_info[num].flags |= TSEC_SGMII; 547 num++; 548 #endif 549 #ifdef CONFIG_TSEC4 550 SET_STD_TSEC_INFO(tsec_info[num], 4); 551 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) 552 tsec_info[num].flags |= TSEC_SGMII; 553 num++; 554 #endif 555 556 if (!num) { 557 printf("No TSECs initialized\n"); 558 559 return 0; 560 } 561 562 fsl_sgmii_riser_init(tsec_info, num); 563 564 tsec_eth_init(bis, tsec_info, num); 565 566 return 0; 567 } 568 #endif 569 570 #if defined(CONFIG_OF_BOARD_SETUP) 571 void ft_board_setup(void *blob, bd_t *bd) 572 { 573 int node, tmp[2]; 574 const char *path; 575 ulong base, size; 576 577 ft_cpu_setup(blob, bd); 578 579 base = getenv_bootm_low(); 580 size = getenv_bootm_size(); 581 582 fdt_fixup_memory(blob, (u64)base, (u64)size); 583 584 node = fdt_path_offset(blob, "/aliases"); 585 tmp[0] = 0; 586 if (node >= 0) { 587 #ifdef CONFIG_PCIE3 588 path = fdt_getprop(blob, node, "pci0", NULL); 589 if (path) { 590 tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno; 591 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 592 } 593 #endif 594 #ifdef CONFIG_PCIE2 595 path = fdt_getprop(blob, node, "pci1", NULL); 596 if (path) { 597 tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; 598 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 599 } 600 #endif 601 #ifdef CONFIG_PCIE1 602 path = fdt_getprop(blob, node, "pci2", NULL); 603 if (path) { 604 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; 605 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 606 } 607 #endif 608 } 609 } 610 #endif 611 612 #ifdef CONFIG_MP 613 extern void cpu_mp_lmb_reserve(struct lmb *lmb); 614 615 void board_lmb_reserve(struct lmb *lmb) 616 { 617 cpu_mp_lmb_reserve(lmb); 618 } 619 #endif 620