1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <asm/fsl_serdes.h> 34 #include <miiphy.h> 35 #include <libfdt.h> 36 #include <fdt_support.h> 37 #include <tsec.h> 38 #include <fsl_mdio.h> 39 #include <netdev.h> 40 41 #include "../common/sgmii_riser.h" 42 43 int checkboard (void) 44 { 45 u8 vboot; 46 u8 *pixis_base = (u8 *)PIXIS_BASE; 47 48 printf("Board: MPC8572DS Sys ID: 0x%02x, " 49 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 50 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 51 in_8(pixis_base + PIXIS_PVER)); 52 53 vboot = in_8(pixis_base + PIXIS_VBOOT); 54 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) { 55 case PIXIS_VBOOT_LBMAP_NOR0: 56 puts ("vBank: 0\n"); 57 break; 58 case PIXIS_VBOOT_LBMAP_PJET: 59 puts ("Promjet\n"); 60 break; 61 case PIXIS_VBOOT_LBMAP_NAND: 62 puts ("NAND\n"); 63 break; 64 case PIXIS_VBOOT_LBMAP_NOR1: 65 puts ("vBank: 1\n"); 66 break; 67 } 68 69 return 0; 70 } 71 72 73 #if !defined(CONFIG_SPD_EEPROM) 74 /* 75 * Fixed sdram init -- doesn't use serial presence detect. 76 */ 77 78 phys_size_t fixed_sdram (void) 79 { 80 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 81 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 82 uint d_init; 83 84 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 85 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 86 87 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 88 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 89 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 90 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 91 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 92 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 93 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 94 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 95 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 96 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 97 98 #if defined (CONFIG_DDR_ECC) 99 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 100 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 101 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 102 #endif 103 asm("sync;isync"); 104 105 udelay(500); 106 107 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 108 109 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 110 d_init = 1; 111 debug("DDR - 1st controller: memory initializing\n"); 112 /* 113 * Poll until memory is initialized. 114 * 512 Meg at 400 might hit this 200 times or so. 115 */ 116 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 117 udelay(1000); 118 } 119 debug("DDR: memory initialized\n\n"); 120 asm("sync; isync"); 121 udelay(500); 122 #endif 123 124 return 512 * 1024 * 1024; 125 } 126 127 #endif 128 129 #ifdef CONFIG_PCI 130 void pci_init_board(void) 131 { 132 struct pci_controller *hose; 133 134 fsl_pcie_init_board(0); 135 136 hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR)); 137 138 if (hose) { 139 u32 temp32; 140 u8 uli_busno = hose->first_busno + 2; 141 142 /* 143 * Activate ULI1575 legacy chip by performing a fake 144 * memory access. Needed to make ULI RTC work. 145 * Device 1d has the first on-board memory BAR. 146 */ 147 pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0), 148 PCI_BASE_ADDRESS_1, &temp32); 149 150 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { 151 void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0), 152 temp32, 4, 0); 153 debug(" uli1572 read to %p\n", p); 154 in_be32(p); 155 } 156 } 157 } 158 #endif 159 160 int board_early_init_r(void) 161 { 162 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 163 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 164 165 /* 166 * Remap Boot flash + PROMJET region to caching-inhibited 167 * so that flash can be erased properly. 168 */ 169 170 /* Flush d-cache and invalidate i-cache of any FLASH data */ 171 flush_dcache(); 172 invalidate_icache(); 173 174 /* invalidate existing TLB entry for flash + promjet */ 175 disable_tlb(flash_esel); 176 177 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 178 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 179 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 180 181 return 0; 182 } 183 184 #ifdef CONFIG_TSEC_ENET 185 int board_eth_init(bd_t *bis) 186 { 187 struct fsl_pq_mdio_info mdio_info; 188 struct tsec_info_struct tsec_info[4]; 189 int num = 0; 190 191 #ifdef CONFIG_TSEC1 192 SET_STD_TSEC_INFO(tsec_info[num], 1); 193 if (is_serdes_configured(SGMII_TSEC1)) { 194 puts("eTSEC1 is in sgmii mode.\n"); 195 tsec_info[num].flags |= TSEC_SGMII; 196 } 197 num++; 198 #endif 199 #ifdef CONFIG_TSEC2 200 SET_STD_TSEC_INFO(tsec_info[num], 2); 201 if (is_serdes_configured(SGMII_TSEC2)) { 202 puts("eTSEC2 is in sgmii mode.\n"); 203 tsec_info[num].flags |= TSEC_SGMII; 204 } 205 num++; 206 #endif 207 #ifdef CONFIG_TSEC3 208 SET_STD_TSEC_INFO(tsec_info[num], 3); 209 if (is_serdes_configured(SGMII_TSEC3)) { 210 puts("eTSEC3 is in sgmii mode.\n"); 211 tsec_info[num].flags |= TSEC_SGMII; 212 } 213 num++; 214 #endif 215 #ifdef CONFIG_TSEC4 216 SET_STD_TSEC_INFO(tsec_info[num], 4); 217 if (is_serdes_configured(SGMII_TSEC4)) { 218 puts("eTSEC4 is in sgmii mode.\n"); 219 tsec_info[num].flags |= TSEC_SGMII; 220 } 221 num++; 222 #endif 223 224 if (!num) { 225 printf("No TSECs initialized\n"); 226 227 return 0; 228 } 229 230 #ifdef CONFIG_FSL_SGMII_RISER 231 fsl_sgmii_riser_init(tsec_info, num); 232 #endif 233 234 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 235 mdio_info.name = DEFAULT_MII_NAME; 236 fsl_pq_mdio_init(bis, &mdio_info); 237 238 tsec_eth_init(bis, tsec_info, num); 239 240 return pci_eth_init(bis); 241 } 242 #endif 243 244 #if defined(CONFIG_OF_BOARD_SETUP) 245 void ft_board_setup(void *blob, bd_t *bd) 246 { 247 phys_addr_t base; 248 phys_size_t size; 249 250 ft_cpu_setup(blob, bd); 251 252 base = getenv_bootm_low(); 253 size = getenv_bootm_size(); 254 255 fdt_fixup_memory(blob, (u64)base, (u64)size); 256 257 FT_FSL_PCI_SETUP; 258 259 #ifdef CONFIG_FSL_SGMII_RISER 260 fsl_sgmii_riser_fdt_fixup(blob); 261 #endif 262 } 263 #endif 264