1 /* 2 * Copyright 2007-2008 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/immap_85xx.h> 29 #include <asm/immap_fsl_pci.h> 30 #include <asm/fsl_ddr_sdram.h> 31 #include <asm/io.h> 32 #include <miiphy.h> 33 #include <libfdt.h> 34 #include <fdt_support.h> 35 36 #include "../common/pixis.h" 37 38 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 39 extern void ddr_enable_ecc(unsigned int dram_size); 40 #endif 41 42 long int fixed_sdram(void); 43 44 int checkboard (void) 45 { 46 printf ("Board: MPC8572DS, System ID: 0x%02x, " 47 "System Version: 0x%02x, FPGA Version: 0x%02x\n", 48 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), 49 in8(PIXIS_BASE + PIXIS_PVER)); 50 return 0; 51 } 52 53 phys_size_t initdram(int board_type) 54 { 55 phys_size_t dram_size = 0; 56 57 puts("Initializing...."); 58 59 #ifdef CONFIG_SPD_EEPROM 60 dram_size = fsl_ddr_sdram(); 61 62 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 63 64 dram_size *= 0x100000; 65 #else 66 dram_size = fixed_sdram(); 67 #endif 68 69 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 70 /* 71 * Initialize and enable DDR ECC. 72 */ 73 ddr_enable_ecc(dram_size); 74 #endif 75 puts(" DDR: "); 76 return dram_size; 77 } 78 79 #if !defined(CONFIG_SPD_EEPROM) 80 /* 81 * Fixed sdram init -- doesn't use serial presence detect. 82 */ 83 84 phys_size_t fixed_sdram (void) 85 { 86 volatile immap_t *immap = (immap_t *)CFG_IMMR; 87 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 88 uint d_init; 89 90 ddr->cs0_bnds = CFG_DDR_CS0_BNDS; 91 ddr->cs0_config = CFG_DDR_CS0_CONFIG; 92 93 ddr->timing_cfg_3 = CFG_DDR_TIMING_3; 94 ddr->timing_cfg_0 = CFG_DDR_TIMING_0; 95 ddr->timing_cfg_1 = CFG_DDR_TIMING_1; 96 ddr->timing_cfg_2 = CFG_DDR_TIMING_2; 97 ddr->sdram_mode = CFG_DDR_MODE_1; 98 ddr->sdram_mode_2 = CFG_DDR_MODE_2; 99 ddr->sdram_interval = CFG_DDR_INTERVAL; 100 ddr->sdram_data_init = CFG_DDR_DATA_INIT; 101 ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; 102 ddr->sdram_cfg_2 = CFG_DDR_CONTROL2; 103 104 #if defined (CONFIG_DDR_ECC) 105 ddr->err_int_en = CFG_DDR_ERR_INT_EN; 106 ddr->err_disable = CFG_DDR_ERR_DIS; 107 ddr->err_sbe = CFG_DDR_SBE; 108 #endif 109 asm("sync;isync"); 110 111 udelay(500); 112 113 ddr->sdram_cfg = CFG_DDR_CONTROL; 114 115 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 116 d_init = 1; 117 debug("DDR - 1st controller: memory initializing\n"); 118 /* 119 * Poll until memory is initialized. 120 * 512 Meg at 400 might hit this 200 times or so. 121 */ 122 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 123 udelay(1000); 124 } 125 debug("DDR: memory initialized\n\n"); 126 asm("sync; isync"); 127 udelay(500); 128 #endif 129 130 return 512 * 1024 * 1024; 131 } 132 133 #endif 134 135 #ifdef CONFIG_PCIE1 136 static struct pci_controller pcie1_hose; 137 #endif 138 139 #ifdef CONFIG_PCIE2 140 static struct pci_controller pcie2_hose; 141 #endif 142 143 #ifdef CONFIG_PCIE3 144 static struct pci_controller pcie3_hose; 145 #endif 146 147 int first_free_busno=0; 148 #ifdef CONFIG_PCI 149 void pci_init_board(void) 150 { 151 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 152 uint devdisr = gur->devdisr; 153 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 154 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 155 156 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", 157 devdisr, io_sel, host_agent); 158 159 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 160 printf (" eTSEC1 is in sgmii mode.\n"); 161 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) 162 printf (" eTSEC2 is in sgmii mode.\n"); 163 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 164 printf (" eTSEC3 is in sgmii mode.\n"); 165 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) 166 printf (" eTSEC4 is in sgmii mode.\n"); 167 168 169 #ifdef CONFIG_PCIE3 170 { 171 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR; 172 extern void fsl_pci_init(struct pci_controller *hose); 173 struct pci_controller *hose = &pcie3_hose; 174 int pcie_ep = (host_agent == 0) || (host_agent == 3) || 175 (host_agent == 5) || (host_agent == 6); 176 int pcie_configured = io_sel >= 1; 177 u32 temp32; 178 179 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 180 printf ("\n PCIE3 connected to ULI as %s (base address %x)", 181 pcie_ep ? "End Point" : "Root Complex", 182 (uint)pci); 183 if (pci->pme_msg_det) { 184 pci->pme_msg_det = 0xffffffff; 185 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 186 } 187 printf ("\n"); 188 189 /* inbound */ 190 pci_set_region(hose->regions + 0, 191 CFG_PCI_MEMORY_BUS, 192 CFG_PCI_MEMORY_PHYS, 193 CFG_PCI_MEMORY_SIZE, 194 PCI_REGION_MEM | PCI_REGION_MEMORY); 195 196 /* outbound memory */ 197 pci_set_region(hose->regions + 1, 198 CFG_PCIE3_MEM_BASE, 199 CFG_PCIE3_MEM_PHYS, 200 CFG_PCIE3_MEM_SIZE, 201 PCI_REGION_MEM); 202 203 /* outbound io */ 204 pci_set_region(hose->regions + 2, 205 CFG_PCIE3_IO_BASE, 206 CFG_PCIE3_IO_PHYS, 207 CFG_PCIE3_IO_SIZE, 208 PCI_REGION_IO); 209 210 hose->region_count = 3; 211 hose->first_busno=first_free_busno; 212 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 213 214 fsl_pci_init(hose); 215 216 first_free_busno=hose->last_busno+1; 217 printf (" PCIE3 on bus %02x - %02x\n", 218 hose->first_busno,hose->last_busno); 219 220 /* 221 * Activate ULI1575 legacy chip by performing a fake 222 * memory access. Needed to make ULI RTC work. 223 * Device 1d has the first on-board memory BAR. 224 */ 225 226 pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ), 227 PCI_BASE_ADDRESS_1, &temp32); 228 if (temp32 >= CFG_PCIE3_MEM_PHYS) { 229 debug(" uli1572 read to %x\n", temp32); 230 in_be32((unsigned *)temp32); 231 } 232 } else { 233 printf (" PCIE3: disabled\n"); 234 } 235 236 } 237 #else 238 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ 239 #endif 240 241 #ifdef CONFIG_PCIE2 242 { 243 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR; 244 extern void fsl_pci_init(struct pci_controller *hose); 245 struct pci_controller *hose = &pcie2_hose; 246 int pcie_ep = (host_agent == 2) || (host_agent == 4) || 247 (host_agent == 6); 248 int pcie_configured = io_sel & 4; 249 250 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 251 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", 252 pcie_ep ? "End Point" : "Root Complex", 253 (uint)pci); 254 if (pci->pme_msg_det) { 255 pci->pme_msg_det = 0xffffffff; 256 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 257 } 258 printf ("\n"); 259 260 /* inbound */ 261 pci_set_region(hose->regions + 0, 262 CFG_PCI_MEMORY_BUS, 263 CFG_PCI_MEMORY_PHYS, 264 CFG_PCI_MEMORY_SIZE, 265 PCI_REGION_MEM | PCI_REGION_MEMORY); 266 267 /* outbound memory */ 268 pci_set_region(hose->regions + 1, 269 CFG_PCIE2_MEM_BASE, 270 CFG_PCIE2_MEM_PHYS, 271 CFG_PCIE2_MEM_SIZE, 272 PCI_REGION_MEM); 273 274 /* outbound io */ 275 pci_set_region(hose->regions + 2, 276 CFG_PCIE2_IO_BASE, 277 CFG_PCIE2_IO_PHYS, 278 CFG_PCIE2_IO_SIZE, 279 PCI_REGION_IO); 280 281 hose->region_count = 3; 282 hose->first_busno=first_free_busno; 283 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 284 285 fsl_pci_init(hose); 286 first_free_busno=hose->last_busno+1; 287 printf (" PCIE2 on bus %02x - %02x\n", 288 hose->first_busno,hose->last_busno); 289 290 } else { 291 printf (" PCIE2: disabled\n"); 292 } 293 294 } 295 #else 296 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ 297 #endif 298 #ifdef CONFIG_PCIE1 299 { 300 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; 301 extern void fsl_pci_init(struct pci_controller *hose); 302 struct pci_controller *hose = &pcie1_hose; 303 int pcie_ep = (host_agent == 1) || (host_agent == 4) || 304 (host_agent == 5); 305 int pcie_configured = io_sel & 6; 306 307 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 308 printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)", 309 pcie_ep ? "End Point" : "Root Complex", 310 (uint)pci); 311 if (pci->pme_msg_det) { 312 pci->pme_msg_det = 0xffffffff; 313 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 314 } 315 printf ("\n"); 316 317 /* inbound */ 318 pci_set_region(hose->regions + 0, 319 CFG_PCI_MEMORY_BUS, 320 CFG_PCI_MEMORY_PHYS, 321 CFG_PCI_MEMORY_SIZE, 322 PCI_REGION_MEM | PCI_REGION_MEMORY); 323 324 /* outbound memory */ 325 pci_set_region(hose->regions + 1, 326 CFG_PCIE1_MEM_BASE, 327 CFG_PCIE1_MEM_PHYS, 328 CFG_PCIE1_MEM_SIZE, 329 PCI_REGION_MEM); 330 331 /* outbound io */ 332 pci_set_region(hose->regions + 2, 333 CFG_PCIE1_IO_BASE, 334 CFG_PCIE1_IO_PHYS, 335 CFG_PCIE1_IO_SIZE, 336 PCI_REGION_IO); 337 338 hose->region_count = 3; 339 hose->first_busno=first_free_busno; 340 341 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 342 343 fsl_pci_init(hose); 344 345 first_free_busno=hose->last_busno+1; 346 printf(" PCIE1 on bus %02x - %02x\n", 347 hose->first_busno,hose->last_busno); 348 349 } else { 350 printf (" PCIE1: disabled\n"); 351 } 352 353 } 354 #else 355 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 356 #endif 357 } 358 #endif 359 360 int board_early_init_r(void) 361 { 362 unsigned int i; 363 const unsigned int flashbase = CFG_FLASH_BASE; 364 const u8 flash_esel = 2; 365 366 /* 367 * Remap Boot flash + PROMJET region to caching-inhibited 368 * so that flash can be erased properly. 369 */ 370 371 /* Invalidate any remaining lines of the flash from caches. */ 372 for (i = 0; i < 256*1024*1024; i+=32) { 373 asm volatile ("dcbi %0,%1": : "b" (flashbase), "r" (i)); 374 asm volatile ("icbi %0,%1": : "b" (flashbase), "r" (i)); 375 } 376 377 /* invalidate existing TLB entry for flash + promjet */ 378 disable_tlb(flash_esel); 379 380 set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */ 381 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 382 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 383 384 return 0; 385 } 386 387 #ifdef CONFIG_GET_CLK_FROM_ICS307 388 /* decode S[0-2] to Output Divider (OD) */ 389 static unsigned char ics307_S_to_OD[] = { 390 10, 2, 8, 4, 5, 7, 3, 6 391 }; 392 393 /* Calculate frequency being generated by ICS307-02 clock chip based upon 394 * the control bytes being programmed into it. */ 395 /* XXX: This function should probably go into a common library */ 396 static unsigned long 397 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) 398 { 399 const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ; 400 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 401 unsigned long RDW = cw2 & 0x7F; 402 unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; 403 unsigned long freq; 404 405 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ 406 407 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 408 * cw1: V8 V7 V6 V5 V4 V3 V2 V1 409 * cw2: V0 R6 R5 R4 R3 R2 R1 R0 410 * 411 * R6:R0 = Reference Divider Word (RDW) 412 * V8:V0 = VCO Divider Word (VDW) 413 * S2:S0 = Output Divider Select (OD) 414 * F1:F0 = Function of CLK2 Output 415 * TTL = duty cycle 416 * C1:C0 = internal load capacitance for cyrstal 417 */ 418 419 /* Adding 1 to get a "nicely" rounded number, but this needs 420 * more tweaking to get a "properly" rounded number. */ 421 422 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); 423 424 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, 425 freq); 426 return freq; 427 } 428 429 unsigned long get_board_sys_clk(ulong dummy) 430 { 431 return ics307_clk_freq ( 432 in8(PIXIS_BASE + PIXIS_VSYSCLK0), 433 in8(PIXIS_BASE + PIXIS_VSYSCLK1), 434 in8(PIXIS_BASE + PIXIS_VSYSCLK2) 435 ); 436 } 437 438 unsigned long get_board_ddr_clk(ulong dummy) 439 { 440 return ics307_clk_freq ( 441 in8(PIXIS_BASE + PIXIS_VDDRCLK0), 442 in8(PIXIS_BASE + PIXIS_VDDRCLK1), 443 in8(PIXIS_BASE + PIXIS_VDDRCLK2) 444 ); 445 } 446 #else 447 unsigned long get_board_sys_clk(ulong dummy) 448 { 449 u8 i; 450 ulong val = 0; 451 452 i = in8(PIXIS_BASE + PIXIS_SPD); 453 i &= 0x07; 454 455 switch (i) { 456 case 0: 457 val = 33333333; 458 break; 459 case 1: 460 val = 40000000; 461 break; 462 case 2: 463 val = 50000000; 464 break; 465 case 3: 466 val = 66666666; 467 break; 468 case 4: 469 val = 83333333; 470 break; 471 case 5: 472 val = 100000000; 473 break; 474 case 6: 475 val = 133333333; 476 break; 477 case 7: 478 val = 166666666; 479 break; 480 } 481 482 return val; 483 } 484 485 unsigned long get_board_ddr_clk(ulong dummy) 486 { 487 u8 i; 488 ulong val = 0; 489 490 i = in8(PIXIS_BASE + PIXIS_SPD); 491 i &= 0x38; 492 i >>= 3; 493 494 switch (i) { 495 case 0: 496 val = 33333333; 497 break; 498 case 1: 499 val = 40000000; 500 break; 501 case 2: 502 val = 50000000; 503 break; 504 case 3: 505 val = 66666666; 506 break; 507 case 4: 508 val = 83333333; 509 break; 510 case 5: 511 val = 100000000; 512 break; 513 case 6: 514 val = 133333333; 515 break; 516 case 7: 517 val = 166666666; 518 break; 519 } 520 return val; 521 } 522 #endif 523 524 #if defined(CONFIG_OF_BOARD_SETUP) 525 void ft_board_setup(void *blob, bd_t *bd) 526 { 527 int node, tmp[2]; 528 const char *path; 529 ulong base, size; 530 531 ft_cpu_setup(blob, bd); 532 533 base = getenv_bootm_low(); 534 size = getenv_bootm_size(); 535 536 fdt_fixup_memory(blob, (u64)base, (u64)size); 537 538 node = fdt_path_offset(blob, "/aliases"); 539 tmp[0] = 0; 540 if (node >= 0) { 541 #ifdef CONFIG_PCIE3 542 path = fdt_getprop(blob, node, "pci0", NULL); 543 if (path) { 544 tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno; 545 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 546 } 547 #endif 548 #ifdef CONFIG_PCIE2 549 path = fdt_getprop(blob, node, "pci1", NULL); 550 if (path) { 551 tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; 552 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 553 } 554 #endif 555 #ifdef CONFIG_PCIE1 556 path = fdt_getprop(blob, node, "pci2", NULL); 557 if (path) { 558 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; 559 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 560 } 561 #endif 562 } 563 } 564 #endif 565 566 #ifdef CONFIG_MP 567 extern void cpu_mp_lmb_reserve(struct lmb *lmb); 568 569 void board_lmb_reserve(struct lmb *lmb) 570 { 571 cpu_mp_lmb_reserve(lmb); 572 } 573 #endif 574