1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <asm/fsl_serdes.h> 34 #include <miiphy.h> 35 #include <libfdt.h> 36 #include <fdt_support.h> 37 #include <tsec.h> 38 #include <fsl_mdio.h> 39 #include <netdev.h> 40 41 #include "../common/sgmii_riser.h" 42 43 int checkboard (void) 44 { 45 u8 vboot; 46 u8 *pixis_base = (u8 *)PIXIS_BASE; 47 48 puts ("Board: MPC8572DS "); 49 #ifdef CONFIG_PHYS_64BIT 50 puts ("(36-bit addrmap) "); 51 #endif 52 printf ("Sys ID: 0x%02x, " 53 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 54 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 55 in_8(pixis_base + PIXIS_PVER)); 56 57 vboot = in_8(pixis_base + PIXIS_VBOOT); 58 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) { 59 case PIXIS_VBOOT_LBMAP_NOR0: 60 puts ("vBank: 0\n"); 61 break; 62 case PIXIS_VBOOT_LBMAP_PJET: 63 puts ("Promjet\n"); 64 break; 65 case PIXIS_VBOOT_LBMAP_NAND: 66 puts ("NAND\n"); 67 break; 68 case PIXIS_VBOOT_LBMAP_NOR1: 69 puts ("vBank: 1\n"); 70 break; 71 } 72 73 return 0; 74 } 75 76 77 #if !defined(CONFIG_SPD_EEPROM) 78 /* 79 * Fixed sdram init -- doesn't use serial presence detect. 80 */ 81 82 phys_size_t fixed_sdram (void) 83 { 84 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 85 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 86 uint d_init; 87 88 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 89 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 90 91 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 92 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 93 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 94 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 95 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 96 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 97 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 98 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 99 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 100 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 101 102 #if defined (CONFIG_DDR_ECC) 103 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 104 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 105 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 106 #endif 107 asm("sync;isync"); 108 109 udelay(500); 110 111 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 112 113 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 114 d_init = 1; 115 debug("DDR - 1st controller: memory initializing\n"); 116 /* 117 * Poll until memory is initialized. 118 * 512 Meg at 400 might hit this 200 times or so. 119 */ 120 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 121 udelay(1000); 122 } 123 debug("DDR: memory initialized\n\n"); 124 asm("sync; isync"); 125 udelay(500); 126 #endif 127 128 return 512 * 1024 * 1024; 129 } 130 131 #endif 132 133 #ifdef CONFIG_PCI 134 void pci_init_board(void) 135 { 136 struct pci_controller *hose; 137 138 fsl_pcie_init_board(0); 139 140 hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR)); 141 142 if (hose) { 143 u32 temp32; 144 u8 uli_busno = hose->first_busno + 2; 145 146 /* 147 * Activate ULI1575 legacy chip by performing a fake 148 * memory access. Needed to make ULI RTC work. 149 * Device 1d has the first on-board memory BAR. 150 */ 151 pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0), 152 PCI_BASE_ADDRESS_1, &temp32); 153 154 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { 155 void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0), 156 temp32, 4, 0); 157 debug(" uli1572 read to %p\n", p); 158 in_be32(p); 159 } 160 } 161 } 162 #endif 163 164 int board_early_init_r(void) 165 { 166 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 167 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 168 169 /* 170 * Remap Boot flash + PROMJET region to caching-inhibited 171 * so that flash can be erased properly. 172 */ 173 174 /* Flush d-cache and invalidate i-cache of any FLASH data */ 175 flush_dcache(); 176 invalidate_icache(); 177 178 /* invalidate existing TLB entry for flash + promjet */ 179 disable_tlb(flash_esel); 180 181 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 182 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 183 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 184 185 return 0; 186 } 187 188 #ifdef CONFIG_TSEC_ENET 189 int board_eth_init(bd_t *bis) 190 { 191 struct fsl_pq_mdio_info mdio_info; 192 struct tsec_info_struct tsec_info[4]; 193 int num = 0; 194 195 #ifdef CONFIG_TSEC1 196 SET_STD_TSEC_INFO(tsec_info[num], 1); 197 if (is_serdes_configured(SGMII_TSEC1)) { 198 puts("eTSEC1 is in sgmii mode.\n"); 199 tsec_info[num].flags |= TSEC_SGMII; 200 } 201 num++; 202 #endif 203 #ifdef CONFIG_TSEC2 204 SET_STD_TSEC_INFO(tsec_info[num], 2); 205 if (is_serdes_configured(SGMII_TSEC2)) { 206 puts("eTSEC2 is in sgmii mode.\n"); 207 tsec_info[num].flags |= TSEC_SGMII; 208 } 209 num++; 210 #endif 211 #ifdef CONFIG_TSEC3 212 SET_STD_TSEC_INFO(tsec_info[num], 3); 213 if (is_serdes_configured(SGMII_TSEC3)) { 214 puts("eTSEC3 is in sgmii mode.\n"); 215 tsec_info[num].flags |= TSEC_SGMII; 216 } 217 num++; 218 #endif 219 #ifdef CONFIG_TSEC4 220 SET_STD_TSEC_INFO(tsec_info[num], 4); 221 if (is_serdes_configured(SGMII_TSEC4)) { 222 puts("eTSEC4 is in sgmii mode.\n"); 223 tsec_info[num].flags |= TSEC_SGMII; 224 } 225 num++; 226 #endif 227 228 if (!num) { 229 printf("No TSECs initialized\n"); 230 231 return 0; 232 } 233 234 #ifdef CONFIG_FSL_SGMII_RISER 235 fsl_sgmii_riser_init(tsec_info, num); 236 #endif 237 238 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 239 mdio_info.name = DEFAULT_MII_NAME; 240 fsl_pq_mdio_init(bis, &mdio_info); 241 242 tsec_eth_init(bis, tsec_info, num); 243 244 return pci_eth_init(bis); 245 } 246 #endif 247 248 #if defined(CONFIG_OF_BOARD_SETUP) 249 void ft_board_setup(void *blob, bd_t *bd) 250 { 251 phys_addr_t base; 252 phys_size_t size; 253 254 ft_cpu_setup(blob, bd); 255 256 base = getenv_bootm_low(); 257 size = getenv_bootm_size(); 258 259 fdt_fixup_memory(blob, (u64)base, (u64)size); 260 261 FT_FSL_PCI_SETUP; 262 263 #ifdef CONFIG_FSL_SGMII_RISER 264 fsl_sgmii_riser_fdt_fixup(blob); 265 #endif 266 } 267 #endif 268