1 /* 2 * Copyright 2007-2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <asm/fsl_serdes.h> 34 #include <miiphy.h> 35 #include <libfdt.h> 36 #include <fdt_support.h> 37 #include <tsec.h> 38 #include <netdev.h> 39 40 #include "../common/sgmii_riser.h" 41 42 int checkboard (void) 43 { 44 u8 vboot; 45 u8 *pixis_base = (u8 *)PIXIS_BASE; 46 47 puts ("Board: MPC8572DS "); 48 #ifdef CONFIG_PHYS_64BIT 49 puts ("(36-bit addrmap) "); 50 #endif 51 printf ("Sys ID: 0x%02x, " 52 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 53 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 54 in_8(pixis_base + PIXIS_PVER)); 55 56 vboot = in_8(pixis_base + PIXIS_VBOOT); 57 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) { 58 case PIXIS_VBOOT_LBMAP_NOR0: 59 puts ("vBank: 0\n"); 60 break; 61 case PIXIS_VBOOT_LBMAP_PJET: 62 puts ("Promjet\n"); 63 break; 64 case PIXIS_VBOOT_LBMAP_NAND: 65 puts ("NAND\n"); 66 break; 67 case PIXIS_VBOOT_LBMAP_NOR1: 68 puts ("vBank: 1\n"); 69 break; 70 } 71 72 return 0; 73 } 74 75 76 #if !defined(CONFIG_SPD_EEPROM) 77 /* 78 * Fixed sdram init -- doesn't use serial presence detect. 79 */ 80 81 phys_size_t fixed_sdram (void) 82 { 83 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 84 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 85 uint d_init; 86 87 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 88 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 89 90 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 91 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 92 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 93 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 94 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 95 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 96 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 97 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 98 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 99 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 100 101 #if defined (CONFIG_DDR_ECC) 102 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 103 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 104 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 105 #endif 106 asm("sync;isync"); 107 108 udelay(500); 109 110 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 111 112 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 113 d_init = 1; 114 debug("DDR - 1st controller: memory initializing\n"); 115 /* 116 * Poll until memory is initialized. 117 * 512 Meg at 400 might hit this 200 times or so. 118 */ 119 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 120 udelay(1000); 121 } 122 debug("DDR: memory initialized\n\n"); 123 asm("sync; isync"); 124 udelay(500); 125 #endif 126 127 return 512 * 1024 * 1024; 128 } 129 130 #endif 131 132 #ifdef CONFIG_PCI 133 void pci_init_board(void) 134 { 135 struct pci_controller *hose; 136 137 fsl_pcie_init_board(0); 138 139 hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR)); 140 141 if (hose) { 142 u32 temp32; 143 u8 uli_busno = hose->first_busno + 2; 144 145 /* 146 * Activate ULI1575 legacy chip by performing a fake 147 * memory access. Needed to make ULI RTC work. 148 * Device 1d has the first on-board memory BAR. 149 */ 150 pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0), 151 PCI_BASE_ADDRESS_1, &temp32); 152 153 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { 154 void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0), 155 temp32, 4, 0); 156 debug(" uli1572 read to %p\n", p); 157 in_be32(p); 158 } 159 } 160 } 161 #endif 162 163 int board_early_init_r(void) 164 { 165 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 166 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 167 168 /* 169 * Remap Boot flash + PROMJET region to caching-inhibited 170 * so that flash can be erased properly. 171 */ 172 173 /* Flush d-cache and invalidate i-cache of any FLASH data */ 174 flush_dcache(); 175 invalidate_icache(); 176 177 /* invalidate existing TLB entry for flash + promjet */ 178 disable_tlb(flash_esel); 179 180 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 181 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 182 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 183 184 return 0; 185 } 186 187 #ifdef CONFIG_TSEC_ENET 188 int board_eth_init(bd_t *bis) 189 { 190 struct tsec_info_struct tsec_info[4]; 191 int num = 0; 192 193 #ifdef CONFIG_TSEC1 194 SET_STD_TSEC_INFO(tsec_info[num], 1); 195 if (is_serdes_configured(SGMII_TSEC1)) { 196 puts("eTSEC1 is in sgmii mode.\n"); 197 tsec_info[num].flags |= TSEC_SGMII; 198 } 199 num++; 200 #endif 201 #ifdef CONFIG_TSEC2 202 SET_STD_TSEC_INFO(tsec_info[num], 2); 203 if (is_serdes_configured(SGMII_TSEC2)) { 204 puts("eTSEC2 is in sgmii mode.\n"); 205 tsec_info[num].flags |= TSEC_SGMII; 206 } 207 num++; 208 #endif 209 #ifdef CONFIG_TSEC3 210 SET_STD_TSEC_INFO(tsec_info[num], 3); 211 if (is_serdes_configured(SGMII_TSEC3)) { 212 puts("eTSEC3 is in sgmii mode.\n"); 213 tsec_info[num].flags |= TSEC_SGMII; 214 } 215 num++; 216 #endif 217 #ifdef CONFIG_TSEC4 218 SET_STD_TSEC_INFO(tsec_info[num], 4); 219 if (is_serdes_configured(SGMII_TSEC4)) { 220 puts("eTSEC4 is in sgmii mode.\n"); 221 tsec_info[num].flags |= TSEC_SGMII; 222 } 223 num++; 224 #endif 225 226 if (!num) { 227 printf("No TSECs initialized\n"); 228 229 return 0; 230 } 231 232 #ifdef CONFIG_FSL_SGMII_RISER 233 fsl_sgmii_riser_init(tsec_info, num); 234 #endif 235 236 tsec_eth_init(bis, tsec_info, num); 237 238 return pci_eth_init(bis); 239 } 240 #endif 241 242 #if defined(CONFIG_OF_BOARD_SETUP) 243 void ft_board_setup(void *blob, bd_t *bd) 244 { 245 phys_addr_t base; 246 phys_size_t size; 247 248 ft_cpu_setup(blob, bd); 249 250 base = getenv_bootm_low(); 251 size = getenv_bootm_size(); 252 253 fdt_fixup_memory(blob, (u64)base, (u64)size); 254 255 FT_FSL_PCI_SETUP; 256 257 #ifdef CONFIG_FSL_SGMII_RISER 258 fsl_sgmii_riser_fdt_fixup(blob); 259 #endif 260 } 261 #endif 262 263 #ifdef CONFIG_MP 264 extern void cpu_mp_lmb_reserve(struct lmb *lmb); 265 266 void board_lmb_reserve(struct lmb *lmb) 267 { 268 cpu_mp_lmb_reserve(lmb); 269 } 270 #endif 271