1 /* 2 * Copyright 2007-2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <miiphy.h> 34 #include <libfdt.h> 35 #include <fdt_support.h> 36 #include <tsec.h> 37 #include <netdev.h> 38 39 #include "../common/sgmii_riser.h" 40 41 long int fixed_sdram(void); 42 43 int checkboard (void) 44 { 45 u8 vboot; 46 u8 *pixis_base = (u8 *)PIXIS_BASE; 47 48 puts ("Board: MPC8572DS "); 49 #ifdef CONFIG_PHYS_64BIT 50 puts ("(36-bit addrmap) "); 51 #endif 52 printf ("Sys ID: 0x%02x, " 53 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 54 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 55 in_8(pixis_base + PIXIS_PVER)); 56 57 vboot = in_8(pixis_base + PIXIS_VBOOT); 58 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) { 59 case PIXIS_VBOOT_LBMAP_NOR0: 60 puts ("vBank: 0\n"); 61 break; 62 case PIXIS_VBOOT_LBMAP_PJET: 63 puts ("Promjet\n"); 64 break; 65 case PIXIS_VBOOT_LBMAP_NAND: 66 puts ("NAND\n"); 67 break; 68 case PIXIS_VBOOT_LBMAP_NOR1: 69 puts ("vBank: 1\n"); 70 break; 71 } 72 73 return 0; 74 } 75 76 phys_size_t initdram(int board_type) 77 { 78 phys_size_t dram_size = 0; 79 80 puts("Initializing...."); 81 82 #ifdef CONFIG_SPD_EEPROM 83 dram_size = fsl_ddr_sdram(); 84 #else 85 dram_size = fixed_sdram(); 86 #endif 87 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 88 dram_size *= 0x100000; 89 90 puts(" DDR: "); 91 return dram_size; 92 } 93 94 #if !defined(CONFIG_SPD_EEPROM) 95 /* 96 * Fixed sdram init -- doesn't use serial presence detect. 97 */ 98 99 phys_size_t fixed_sdram (void) 100 { 101 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 102 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 103 uint d_init; 104 105 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 106 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 107 108 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 109 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 110 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 111 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 112 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 113 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 114 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 115 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 116 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 117 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 118 119 #if defined (CONFIG_DDR_ECC) 120 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 121 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 122 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 123 #endif 124 asm("sync;isync"); 125 126 udelay(500); 127 128 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 129 130 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 131 d_init = 1; 132 debug("DDR - 1st controller: memory initializing\n"); 133 /* 134 * Poll until memory is initialized. 135 * 512 Meg at 400 might hit this 200 times or so. 136 */ 137 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 138 udelay(1000); 139 } 140 debug("DDR: memory initialized\n\n"); 141 asm("sync; isync"); 142 udelay(500); 143 #endif 144 145 return 512 * 1024 * 1024; 146 } 147 148 #endif 149 150 #ifdef CONFIG_PCIE1 151 static struct pci_controller pcie1_hose; 152 #endif 153 154 #ifdef CONFIG_PCIE2 155 static struct pci_controller pcie2_hose; 156 #endif 157 158 #ifdef CONFIG_PCIE3 159 static struct pci_controller pcie3_hose; 160 #endif 161 162 #ifdef CONFIG_PCI 163 void pci_init_board(void) 164 { 165 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 166 struct fsl_pci_info pci_info[3]; 167 u32 devdisr, pordevsr, io_sel, temp32; 168 int first_free_busno = 0; 169 int num = 0; 170 171 int pcie_ep, pcie_configured; 172 173 devdisr = in_be32(&gur->devdisr); 174 pordevsr = in_be32(&gur->pordevsr); 175 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 176 177 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 178 179 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 180 printf (" eTSEC1 is in sgmii mode.\n"); 181 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) 182 printf (" eTSEC2 is in sgmii mode.\n"); 183 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 184 printf (" eTSEC3 is in sgmii mode.\n"); 185 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) 186 printf (" eTSEC4 is in sgmii mode.\n"); 187 188 puts("\n"); 189 #ifdef CONFIG_PCIE3 190 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); 191 192 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ 193 SET_STD_PCIE_INFO(pci_info[num], 3); 194 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); 195 printf (" PCIE3 connected to ULI as %s (base addr %lx)\n", 196 pcie_ep ? "Endpoint" : "Root Complex", 197 pci_info[num].regs); 198 first_free_busno = fsl_pci_init_port(&pci_info[num++], 199 &pcie3_hose, first_free_busno); 200 /* 201 * Activate ULI1575 legacy chip by performing a fake 202 * memory access. Needed to make ULI RTC work. 203 * Device 1d has the first on-board memory BAR. 204 */ 205 pci_hose_read_config_dword(&pcie3_hose, PCI_BDF(2, 0x1d, 0), 206 PCI_BASE_ADDRESS_1, &temp32); 207 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { 208 void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0), 209 temp32, 4, 0); 210 debug(" uli1572 read to %p\n", p); 211 in_be32(p); 212 } 213 } else { 214 printf (" PCIE3: disabled\n"); 215 } 216 puts("\n"); 217 #else 218 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ 219 #endif 220 221 #ifdef CONFIG_PCIE2 222 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); 223 224 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ 225 SET_STD_PCIE_INFO(pci_info[num], 2); 226 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); 227 printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", 228 pcie_ep ? "Endpoint" : "Root Complex", 229 pci_info[num].regs); 230 first_free_busno = fsl_pci_init_port(&pci_info[num++], 231 &pcie2_hose, first_free_busno); 232 } else { 233 printf (" PCIE2: disabled\n"); 234 } 235 236 puts("\n"); 237 #else 238 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ 239 #endif 240 241 #ifdef CONFIG_PCIE1 242 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 243 244 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 245 SET_STD_PCIE_INFO(pci_info[num], 1); 246 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 247 printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", 248 pcie_ep ? "Endpoint" : "Root Complex", 249 pci_info[num].regs); 250 first_free_busno = fsl_pci_init_port(&pci_info[num++], 251 &pcie1_hose, first_free_busno); 252 } else { 253 printf (" PCIE1: disabled\n"); 254 } 255 256 puts("\n"); 257 #else 258 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 259 #endif 260 } 261 #endif 262 263 int board_early_init_r(void) 264 { 265 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 266 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 267 268 /* 269 * Remap Boot flash + PROMJET region to caching-inhibited 270 * so that flash can be erased properly. 271 */ 272 273 /* Flush d-cache and invalidate i-cache of any FLASH data */ 274 flush_dcache(); 275 invalidate_icache(); 276 277 /* invalidate existing TLB entry for flash + promjet */ 278 disable_tlb(flash_esel); 279 280 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 281 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 282 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 283 284 return 0; 285 } 286 287 #ifdef CONFIG_TSEC_ENET 288 int board_eth_init(bd_t *bis) 289 { 290 struct tsec_info_struct tsec_info[4]; 291 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 292 int num = 0; 293 294 #ifdef CONFIG_TSEC1 295 SET_STD_TSEC_INFO(tsec_info[num], 1); 296 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 297 tsec_info[num].flags |= TSEC_SGMII; 298 num++; 299 #endif 300 #ifdef CONFIG_TSEC2 301 SET_STD_TSEC_INFO(tsec_info[num], 2); 302 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) 303 tsec_info[num].flags |= TSEC_SGMII; 304 num++; 305 #endif 306 #ifdef CONFIG_TSEC3 307 SET_STD_TSEC_INFO(tsec_info[num], 3); 308 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 309 tsec_info[num].flags |= TSEC_SGMII; 310 num++; 311 #endif 312 #ifdef CONFIG_TSEC4 313 SET_STD_TSEC_INFO(tsec_info[num], 4); 314 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) 315 tsec_info[num].flags |= TSEC_SGMII; 316 num++; 317 #endif 318 319 if (!num) { 320 printf("No TSECs initialized\n"); 321 322 return 0; 323 } 324 325 #ifdef CONFIG_FSL_SGMII_RISER 326 fsl_sgmii_riser_init(tsec_info, num); 327 #endif 328 329 tsec_eth_init(bis, tsec_info, num); 330 331 return pci_eth_init(bis); 332 } 333 #endif 334 335 #if defined(CONFIG_OF_BOARD_SETUP) 336 void ft_board_setup(void *blob, bd_t *bd) 337 { 338 phys_addr_t base; 339 phys_size_t size; 340 341 ft_cpu_setup(blob, bd); 342 343 base = getenv_bootm_low(); 344 size = getenv_bootm_size(); 345 346 fdt_fixup_memory(blob, (u64)base, (u64)size); 347 348 FT_FSL_PCI_SETUP; 349 350 #ifdef CONFIG_FSL_SGMII_RISER 351 fsl_sgmii_riser_fdt_fixup(blob); 352 #endif 353 } 354 #endif 355 356 #ifdef CONFIG_MP 357 extern void cpu_mp_lmb_reserve(struct lmb *lmb); 358 359 void board_lmb_reserve(struct lmb *lmb) 360 { 361 cpu_mp_lmb_reserve(lmb); 362 } 363 #endif 364