1 /* 2 * Copyright 2008 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 #include <common.h> 10 11 #include <asm/fsl_ddr_sdram.h> 12 #include <asm/fsl_ddr_dimm_params.h> 13 14 typedef struct { 15 u32 datarate_mhz_low; 16 u32 datarate_mhz_high; 17 u32 n_ranks; 18 u32 clk_adjust; 19 u32 cpo; 20 u32 write_data_delay; 21 u32 force_2T; 22 } board_specific_parameters_t; 23 24 /* 25 * CPO value doesn't matter if workaround for errata 111 and 134 enabled. 26 * 27 * For DDR2 DIMM, all combinations of clk_adjust and write_data_delay have been 28 * tested. For RDIMM, clk_adjust = 4 and write_data_delay = 3 is optimized for 29 * all clocks from 400MT/s to 800MT/s, verified with Kingston KVR800D2D8P6/2G. 30 * For UDIMM, clk_adjust = 8 and write_delay = 5 is optimized for all clocks 31 * from 400MT/s to 800MT/s, verified with Micron MT18HTF25672AY-800E1. 32 */ 33 const board_specific_parameters_t board_specific_parameters_udimm[][20] = { 34 { 35 /* 36 * memory controller 0 37 * lo| hi| num| clk| cpo|wrdata|2T 38 * mhz| mhz|ranks|adjst| | delay| 39 */ 40 { 0, 333, 2, 8, 7, 5, 0}, 41 {334, 400, 2, 8, 9, 5, 0}, 42 {401, 549, 2, 8, 11, 5, 0}, 43 {550, 680, 2, 8, 10, 5, 0}, 44 {681, 850, 2, 8, 12, 5, 1}, 45 { 0, 333, 1, 6, 7, 3, 0}, 46 {334, 400, 1, 6, 9, 3, 0}, 47 {401, 549, 1, 6, 11, 3, 0}, 48 {550, 680, 1, 1, 10, 5, 0}, 49 {681, 850, 1, 1, 12, 5, 0} 50 }, 51 52 { 53 /* 54 * memory controller 1 55 * lo| hi| num| clk| cpo|wrdata|2T 56 * mhz| mhz|ranks|adjst| | delay| 57 */ 58 { 0, 333, 2, 8, 7, 5, 0}, 59 {334, 400, 2, 8, 9, 5, 0}, 60 {401, 549, 2, 8, 11, 5, 0}, 61 {550, 680, 2, 8, 11, 5, 0}, 62 {681, 850, 2, 8, 13, 5, 1}, 63 { 0, 333, 1, 6, 7, 3, 0}, 64 {334, 400, 1, 6, 9, 3, 0}, 65 {401, 549, 1, 6, 11, 3, 0}, 66 {550, 680, 1, 1, 11, 6, 0}, 67 {681, 850, 1, 1, 13, 6, 0} 68 } 69 }; 70 71 const board_specific_parameters_t board_specific_parameters_rdimm[][20] = { 72 { 73 /* 74 * memory controller 0 75 * lo| hi| num| clk| cpo|wrdata|2T 76 * mhz| mhz|ranks|adjst| | delay| 77 */ 78 { 0, 333, 2, 4, 7, 3, 0}, 79 {334, 400, 2, 4, 9, 3, 0}, 80 {401, 549, 2, 4, 11, 3, 0}, 81 {550, 680, 2, 4, 10, 3, 0}, 82 {681, 850, 2, 4, 12, 3, 1}, 83 }, 84 85 { 86 /* 87 * memory controller 1 88 * lo| hi| num| clk| cpo|wrdata|2T 89 * mhz| mhz|ranks|adjst| | delay| 90 */ 91 { 0, 333, 2, 4, 7, 3, 0}, 92 {334, 400, 2, 4, 9, 3, 0}, 93 {401, 549, 2, 4, 11, 3, 0}, 94 {550, 680, 2, 4, 11, 3, 0}, 95 {681, 850, 2, 4, 13, 3, 1}, 96 } 97 }; 98 99 void fsl_ddr_board_options(memctl_options_t *popts, 100 dimm_params_t *pdimm, 101 unsigned int ctrl_num) 102 { 103 const board_specific_parameters_t *pbsp; 104 u32 num_params; 105 u32 i; 106 ulong ddr_freq; 107 108 if (!pdimm->n_ranks) 109 return; 110 111 if (popts->registered_dimm_en) { 112 pbsp = &(board_specific_parameters_rdimm[ctrl_num][0]); 113 num_params = sizeof(board_specific_parameters_rdimm[ctrl_num]) / 114 sizeof(board_specific_parameters_rdimm[0][0]); 115 } else { 116 pbsp = &(board_specific_parameters_udimm[ctrl_num][0]); 117 num_params = sizeof(board_specific_parameters_udimm[ctrl_num]) / 118 sizeof(board_specific_parameters_udimm[0][0]); 119 } 120 121 /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in 122 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If 123 * there are two dimms in the controller, set odt_rd_cfg to 3 and 124 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. 125 */ 126 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 127 if (i&1) { /* odd CS */ 128 popts->cs_local_opts[i].odt_rd_cfg = 0; 129 popts->cs_local_opts[i].odt_wr_cfg = 0; 130 } else { /* even CS */ 131 if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { 132 popts->cs_local_opts[i].odt_rd_cfg = 0; 133 popts->cs_local_opts[i].odt_wr_cfg = 4; 134 } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { 135 popts->cs_local_opts[i].odt_rd_cfg = 3; 136 popts->cs_local_opts[i].odt_wr_cfg = 3; 137 } 138 } 139 } 140 141 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr 142 * freqency and n_banks specified in board_specific_parameters table. 143 */ 144 ddr_freq = get_ddr_freq(0) / 1000000; 145 for (i = 0; i < num_params; i++) { 146 if (ddr_freq >= pbsp->datarate_mhz_low && 147 ddr_freq <= pbsp->datarate_mhz_high && 148 pdimm->n_ranks == pbsp->n_ranks) { 149 popts->clk_adjust = pbsp->clk_adjust; 150 popts->cpo_override = pbsp->cpo; 151 popts->write_data_delay = pbsp->write_data_delay; 152 popts->twoT_en = pbsp->force_2T; 153 break; 154 } 155 pbsp++; 156 } 157 158 if (i == num_params) { 159 printf("Warning: board specific timing not found " 160 "for data rate %lu MT/s!\n", ddr_freq); 161 } 162 163 /* 164 * Factors to consider for half-strength driver enable: 165 * - number of DIMMs installed 166 */ 167 popts->half_strength_driver_enable = 0; 168 } 169